Patents by Inventor Yuuichi Kado

Yuuichi Kado has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Adiabatic charging register circuit
    Patent number: 7030672
    Abstract: An adiabatic charging register circuit comprising a plurality of n-channel MOSFET's and a plurality of p-channel MOSFET's, is operated by a clock signal which has a gradually rising and a gradually falling waveform generated by using a charge recycle power source in which charge supplied to a load is at least partially collected to said charge recycle power source, and following inequality is satisfied; |VTN|+|VTP|?VDD where VTN is threshold of an n-channel MOSFET, VTP is threshold of a p-channel MOSFET, and VDD is output voltage of said charge recycle power source.
    Type: Grant
    Filed: April 27, 2004
    Date of Patent: April 18, 2006
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Shunji Nakata, Yuuichi Kado
  • Adiabatic Charging Register Circuit
    Publication number: 20040189365
    Abstract: An adiabatic charging register circuit comprising a plurality of n-channel MOSFET's and a plurality of p-channel MOSFET's, is operated by a clock signal which has a gradually rising and a gradually falling waveform generated by using a charge recycle power source in which charge supplied to a load is at least partially collected to said charge recycle power source, and following inequality is satisfied;
    Type: Application
    Filed: April 27, 2004
    Publication date: September 30, 2004
    Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Shunji NAKATA, Yuuichi KADO
  • Adiabatic charging register circuit
    Patent number: 6788121
    Abstract: An adiabatic charging register circuit including a plurality of n-channel MOSFET's and plurality of p-channel MOSFET's, is operated by a clock signal which has a gradually rising and an gradually falling waveform generated by using a charge recycle power source in which charge supplied to a load is at lease partially collected to said charge recycle power source, and following inequality is satisfied; |VTN|+|VTP|≧VDD wherein VTN is threshold of an n-channel MOSFET, VTP is threshold of a p-channel MOSFET, and VDD is output voltage of said charge recycle power source.
    Type: Grant
    Filed: June 4, 2001
    Date of Patent: September 7, 2004
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Shunji Nakata, Yuuichi Kado
  • Adiabatic charging register circuit
    Publication number: 20020000862
    Abstract: An adiabatic charging register circuit comprising a plurality of n-channel MOSFET's and a plurality of p-channel MOSFET's, is operated by a clock signal which has a gradually rising and a gradually falling waveform generated by using a charge recycle power source in which charge supplied to a load is at least partially collected to said charge recycle power source, and following inequality is satisfied;
    Type: Application
    Filed: June 4, 2001
    Publication date: January 3, 2002
    Applicant: Nippon Telegraph and Telephone Corporation
    Inventors: Shunji Nakata, Yuuichi Kado