Patents by Inventor Yuuichi Kaji
Yuuichi Kaji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11095278Abstract: A comparator includes: a first amplifying unit that includes a differential pair configured with a pair of transistors which are first and second transistors, and amplifies a difference of signals input to each of the gate electrodes of the first and second transistors, to output; a second amplifying unit that amplifies the signal output from the first amplifying unit; a third transistor that connects the first transistor to a power source voltage; a fourth transistor that connects the second transistor to the power source voltage; a fifth transistor that connects a connection point of gate electrodes of the third transistor and the fourth transistor to a drain of the third transistor; and a sixth transistor that connects a connection point of gate electrodes of the third transistor and the fourth transistor to a drain of the fourth transistor.Type: GrantFiled: April 9, 2018Date of Patent: August 17, 2021Assignee: Sony CorporationInventors: Hideki Tanaka, Shizunori Matsumoto, Haruhisa Naganokawa, Yuuichi Kaji
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Patent number: 10811447Abstract: The present disclosure relates to a solid-state imaging device, a driving method, and electronic equipment that permit imaging of a wide dynamic range image with higher quality. The solid-state imaging device includes a pixel region and a circuit region. A plurality of pixels that perform photoelectric conversion are arranged in the pixel region. At least a logarithmic conversion circuit is arranged in the circuit region. The logarithmic conversion circuit reads out a pixel signal from the pixel through a logarithmic readout scheme in which the pixel signal changes approximately logarithmically in proportion to the amount of light received by the pixel. Also, the logarithmic conversion circuit can switch between a logarithmic readout scheme and a linear readout scheme when the pixel signal is read out from the pixel. The present technology is applicable, for example, to a CMOS image sensor.Type: GrantFiled: February 20, 2017Date of Patent: October 20, 2020Assignee: Sony CorporationInventors: Katsuhiko Hanzawa, Yuuichi Kaji
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Publication number: 20190051680Abstract: The present disclosure relates to a solid-state imaging device, a driving method, and electronic equipment that permit imaging of a wide dynamic range image with higher quality. The solid-state imaging device includes a pixel region and a circuit region. A plurality of pixels that perform photoelectric conversion are arranged in the pixel region. At least a logarithmic conversion circuit is arranged in the circuit region. The logarithmic conversion circuit reads out a pixel signal from the pixel through a logarithmic readout scheme in which the pixel signal changes approximately logarithmically in proportion to the amount of light received by the pixel. Also, the logarithmic conversion circuit can switch between a logarithmic readout scheme and a linear readout scheme when the pixel signal is read out from the pixel. The present technology is applicable, for example, to a CMOS image sensor.Type: ApplicationFiled: February 20, 2017Publication date: February 14, 2019Applicant: Sony CorporationInventors: Katsuhiko Hanzawa, Yuuichi Kaji
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Patent number: 10186512Abstract: [Object] The present technology relates to a solid-state image sensor, image capturing device, and electronic device, capable of setting a reference voltage applied to a vertical transfer line to be substantially the same as a reset voltage of a floating diffusion portion. [Solution] A reference voltage generation circuit configured to generate the reference voltage includes the same circuit as a reset transistor, an amplification transistor, and a selection transistor in a pixel circuit, and applies it to the vertical transfer line immediately before transferring an optical signal and a reset signal. This allows the same reference voltage as that immediately after applying the reset signal to the floating diffusion to be applied to the vertical transfer line. The present technology is applicable to CMOS image sensors.Type: GrantFiled: March 18, 2016Date of Patent: January 22, 2019Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Katsuhiko Hanzawa, Yuuichi Kaji
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Publication number: 20180226962Abstract: A comparator includes: a first amplifying unit that includes a differential pair configured with a pair of transistors which are first and second transistors, and amplifies a difference of signals input to each of the gate electrodes of the first and second transistors, to output; a second amplifying unit that amplifies the signal output from the first amplifying unit; a third transistor that connects the first transistor to a power source voltage; a fourth transistor that connects the second transistor to the power source voltage; a fifth transistor that connects a connection point of gate electrodes of the third transistor and the fourth transistor to a drain of the third transistor; and a sixth transistor that connects a connection point of gate electrodes of the third transistor and the fourth transistor to a drain of the fourth transistor.Type: ApplicationFiled: April 9, 2018Publication date: August 9, 2018Inventors: Hideki Tanaka, Shizunori Matsumoto, Haruhisa Naganokawa, Yuuichi Kaji
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Patent number: 9985622Abstract: A comparator includes: a first amplifying unit that includes a differential pair configured with a pair of transistors which are first and second transistors, and amplifies a difference of signals input to each of the gate electrodes of the first and second transistors, to output; a second amplifying unit that amplifies the signal output from the first amplifying unit; a third transistor that connects the first transistor to a power source voltage; a fourth transistor that connects the second transistor to the power source voltage; a fifth transistor that connects a connection point of gate electrodes of the third transistor and the fourth transistor to a drain of the third transistor; and a sixth transistor that connects a connection point of gate electrodes of the third transistor and the fourth transistor to a drain of the fourth transistor.Type: GrantFiled: March 13, 2014Date of Patent: May 29, 2018Assignee: Sony CorporationInventors: Hideki Tanaka, Shizunori Matsumoto, Haruhisa Naganokawa, Yuuichi Kaji
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Publication number: 20180108658Abstract: [Object] The present technology relates to a solid-state image sensor, image capturing device, and electronic device, capable of setting a reference voltage applied to a vertical transfer line to be substantially the same as a reset voltage of a floating diffusion portion. [Solution] A reference voltage generation circuit configured to generate the reference voltage includes the same circuit as a reset transistor, an amplification transistor, and a selection transistor in a pixel circuit, and applies it to the vertical transfer line immediately before transferring an optical signal and a reset signal. This allows the same reference voltage as that immediately after applying the reset signal to the floating diffusion to be applied to the vertical transfer line. The present technology is applicable to CMOS image sensors.Type: ApplicationFiled: March 18, 2016Publication date: April 19, 2018Inventors: KATSUHIKO HANZAWA, YUUICHI KAJI
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Publication number: 20150237285Abstract: A solid-state imaging device that outputs a pixel signal having a signal level corresponding to charges generated by a photoelectric conversion includes a comparator. The comparator has a first amplifying unit with first and second transistors configured as a differential pair and provides a signal output by amplifying a difference of signals input to the gate electrodes of the first and second transistors. It also has a second amplifying unit that amplifies the signal output, a first condenser disposed between the gate electrode of the first transistor and a reference signal supply, a second condenser disposed between the gate electrode of the second transistor and pixel signal wiring that reads out the pixel signal, and a switching circuit that connects the reference signal supply to the pixel signal wiring.Type: ApplicationFiled: April 29, 2015Publication date: August 20, 2015Inventors: Hideki Tanaka, Shizunori Matsumoto, Haruhisa Naganokawa, Yuuichi Kaji
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Patent number: 9041583Abstract: A comparator includes: a first amplifying unit that includes a differential pair configured with a pair of transistors which are first and second transistors, and amplifies a difference of signals input to each of the gate electrodes of the first and second transistors, to output; a second amplifying unit that amplifies the signal output from the first amplifying unit; a first condenser that is disposed between a gate electrode of the first transistor and a reference signal supply unit; a second condenser that is disposed between a gate electrode of the second transistor and a pixel signal wiring; a third transistor that connects a connection point of the gate electrode of the first transistor and the first condenser to the pixel signal wiring; and a fourth transistor that connects a connection point of the gate electrode of the second transistor and the second condenser to the pixel signal wiring.Type: GrantFiled: March 13, 2014Date of Patent: May 26, 2015Assignee: Sony CorporationInventors: Hideki Tanaka, Shizunori Matsumoto, Haruhisa Naganokawa, Yuuichi Kaji
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Publication number: 20140293104Abstract: A comparator includes: a first amplifying unit that includes a differential pair configured with a pair of transistors which are first and second transistors, and amplifies a difference of signals input to each of the gate electrodes of the first and second transistors, to output; a second amplifying unit that amplifies the signal output from the first amplifying unit; a first condenser that is disposed between a gate electrode of the first transistor and a reference signal supply unit; a second condenser that is disposed between a gate electrode of the second transistor and a pixel signal wiring; a third transistor that connects a connection point of the gate electrode of the first transistor and the first condenser to the pixel signal wiring; and a fourth transistor that connects a connection point of the gate electrode of the second transistor and the second condenser to the pixel signal wiring.Type: ApplicationFiled: March 13, 2014Publication date: October 2, 2014Applicant: SONY CORPORATIONInventors: Hideki Tanaka, Shizunori Matsumoto, Haruhisa Naganokawa, Yuuichi Kaji
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Publication number: 20140291482Abstract: A comparator includes: a first amplifying unit that includes a differential pair configured with a pair of transistors which are first and second transistors, and amplifies a difference of signals input to each of the gate electrodes of the first and second transistors, to output; a second amplifying unit that amplifies the signal output from the first amplifying unit; a third transistor that connects the first transistor to a power source voltage; a fourth transistor that connects the second transistor to the power source voltage; a fifth transistor that connects a connection point of gate electrodes of the third transistor and the fourth transistor to a drain of the third transistor; and a sixth transistor that connects a connection point of gate electrodes of the third transistor and the fourth transistor to a drain of the fourth transistor.Type: ApplicationFiled: March 13, 2014Publication date: October 2, 2014Applicant: SONY CORPORATIONInventors: Hideki Tanaka, Shizunori Matsumoto, Haruhisa Naganokawa, Yuuichi Kaji