Abstract: This stator core is a stator core for a rotating electric machine of an axial gap type and includes a body portion formed by a compaction-molded body of soft magnetic powder whose surfaces are coated with insulating films, wherein the body portion is provided with one or a plurality of through holes.

Abstract: A cache memory apparatus and microprocessor therewith has a first address register for a tag memory and a second address register for a data memory, a tag entry decoder and a data entry decoder. Lower order bits of the contents stored in the first address register are transferred to the second address register through a transferring path in a write operation. Tag comparison and a data write of a result of the preceding comparison are executed in parallel in the same clock period, and thereby speed of processing is higher in the case of consecutive write operations at a write hit.

Abstract: A power supply for use in a computer system according to this invention has a one-chip microcomputer having a built-in A/D converter. The microcomputer, which has a communication function, performs a power off sequence for a computer system and a power off sequence for a hard disk drive built in the computer system, while communicating with the computer system. Further, the microcomputer detects the voltage and current of a chargeable battery, discriminates a low battery state, monitors a power switch, a hard disk drive switch and a reset switch, and monitors an input/output voltage.

Abstract: A microprocessor which has a plurality of cache memory units with plural ways, a plurality of data buses each having different bus width, and a write way control unit or an address control unit whichever capable of switching the number of ways or entries of these cache memory units in accordance with a bus mode determined by a specified data bus and accessing specific cache memory units, where by switching the number of ways or entries in accordance with the set bus mode the byte number of fetched instructions and data is brought into perfect accord with the data width (line size) of respective cache memory units during any bus mode. This in turn fully eliminates unused region of respective cache memory units to provide the improved efficiency of the use of the entire cache memory units.

Abstract: A data processor which is constructed such that, when writing processing of an operand to external devices is included as the last step processing of a microprogram, by moving only the writing processing to a next pipeline stage, all of external access processings during execution of the microinstruction in the other plural steps are executed in an instruction execution stage, thereby information showing the internal states such as PSW, PC, and the like can be managed in the instruction execution stage alone to facilitate exceptional processing.

Abstract: A system for preventing register conflict in a pipeline including a flag group memories at selected stages for storing flag groups indicating which general purpose registers are reserved by the instructions being processed at the selected stages. A flag group associated with a particular instruction is shifted with the instruction through the pipeline.

Abstract: A bypass circuit (20) opens transmission gates (13) through (16) when the condition is satisfied that two bit values Ai and Bi (i=0, 1, . . . n) to each full adder (1) are non-coincident with each other throughout the full adders. To this end, the inverse of the initial carry signal C.sub.0 is outputted as the addition results S.sub.0 and S.sub.n and the initial carry signal C.sub.0 is outputted as the final stage output signal C.sub.n.