Abstract: A watch dog timer (20) is controlled to permit or inhibit operation of a free run counter (3). When a flip-flop (14) is reset by a reset signal, no clock signal is supplied to the free run counter (3), the operation of which is then inhibited. When a microcomputer (1) outputs an address signal (5) and a write signal (6), an address decoder (12) decodes the address signal to open an AND gate (13), thereby to set the flip-flop (14). When the flip-flop (14) is set, and AND gate (17) is opened to supply clock pulses to the free run counter (3), which in turn starts counting the clock pulses. When the microcomputer (1) operates abnormally and no clear signal is supplied to the free run counter (3) from a clear decision circuit (2), the free run counter (3) outputs a signal indicating abnormal operation of the microcomputer (1) upon counting a prescribed counter value.