Abstract: A semiconductor device according to an embodiment includes a semiconductor chip, a semiconductor element, a stacked body, and a structure body. The semiconductor chip includes a first surface, a second surface, and a side surface between the first surface and the second surface. The semiconductor element is provided in the center of the semiconductor chip when viewed from the normal direction of the first surface. The stacked body is provided at the outer peripheral end portion of the semiconductor chip when viewed from the normal direction and includes a plurality of first layers and a plurality of second layers alternately stacked in the normal direction. The structure body is provided in at least a part between the semiconductor element and the side surface when viewed from the normal direction and extending from a position higher than the stacked body to a position lower than the stacked body.

Abstract: A semiconductor device includes: wiring layers laminated in a first direction and including conducting members; and a second wiring layer including a bonding pad electrode. The first wiring layers each include a bonding pad area. The bonding pad area overlaps with the bonding pad electrode viewed in the first direction. The conducting member is absent in an area inside a first imaginary circle with a first point as a midpoint in the bonding pad area. The conducting members are disposed in an area outside a second imaginary circle in the bonding pad area. The second imaginary circle has the first point as a midpoint and has a radius equal to or more than a radius of the first imaginary circle. When the radius of the first imaginary circle is denoted as R1 and the radius of the second imaginary circle is denoted as R2, R2/R1 is smaller than 1/cos(?/4).

Abstract: A semiconductor device includes: wiring layers laminated in a first direction and including conducting members; and a second wiring layer including a bonding pad electrode. The first wiring layers each include a bonding pad area. The bonding pad area overlaps with the bonding pad electrode viewed in the first direction. The conducting member is absent in an area inside a first imaginary circle with a first point as a midpoint in the bonding pad area. The conducting members are disposed in an area outside a second imaginary circle in the bonding pad area. The second imaginary circle has the first point as a midpoint and has a radius equal to or more than a radius of the first imaginary circle. When the radius of the first imaginary circle is denoted as R1 and the radius of the second imaginary circle is denoted as R2, R2/R1 is smaller than 1/cos(?/4).

Abstract: A semiconductor device according to an embodiment, includes a plurality of wires, a first dielectric film, and a second dielectric film. The plurality of wires are arranged above a semiconductor substrate so as to extend in a first direction and aligned via a first cavity. The first dielectric film has a plurality of portions arranged above the plurality of wires so as to extend in a second direction substantially perpendicular to the plurality of wires and aligned along the first direction via a second cavity leading to the first cavity. The second dielectric film is formed above the first dielectric film so as to cover the second cavity.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes first word lines equipped with flag-like portions on one side of the block in the row direction and equipped with no flag-like portions on the other side of the block in the row direction, and second word lines equipped with no flag-like portions on the one side of the block in the row direction and equipped with flag-like portions on the other side of the block in the row direction.

Abstract: A semiconductor device according to an embodiment, includes a plurality of wires, a first dielectric film, and a second dielectric film. The plurality of wires are arranged above a semiconductor substrate so as to extend in a first direction and aligned via a first cavity. The first dielectric film has a plurality of portions arranged above the plurality of wires so as to extend in a second direction substantially perpendicular to the plurality of wires and aligned along the first direction via a second cavity leading to the first cavity. The second dielectric film is formed above the first dielectric film so as to cover the second cavity.

Abstract: A semiconductor device has a circuit element region formed on a semiconductor substrate, and a protective pattern formed so as to surround the circuit element region.

Abstract: A semiconductor device has a circuit element region formed on a semiconductor substrate, and a protective pattern formed so as to surround the circuit element region.

Abstract: A method for manufacturing an industrial product encompasses: forming a intermediate product pattern, which implements a part of a intermediate product of the industrial product by a sequence of processes corresponds to a part of a procedure for manufacturing the industrial product; forming an interconnect-changing insulator on the intermediate product pattern; boring sampling contact holes in the interconnect-changing insulator so as to make bare a part of the intermediate product pattern to define sampling sites; delineating evaluation interconnects on the interconnect-changing insulator so that each of the evaluation interconnects can electrically connected to at least one of the sampling sites of intermediate product pattern; and measuring an electrical resistance between subject sampling sites through the evaluation interconnects so as to detect a product defect in the intermediate product pattern.

Abstract: A method for manufacturing an industrial product encompasses: forming a intermediate product pattern, which implements a part of a intermediate product of the industrial product by a sequence of processes corresponds to a part of a procedure for manufacturing the industrial product; forming an interconnect-changing insulator on the intermediate product pattern; boring sampling contact holes in the interconnect-changing insulator so as to make bare a part of the intermediate product pattern to define sampling sites; delineating evaluation interconnects on the interconnect-changing insulator so that each of the evaluation interconnects can electrically connected to at least one of the sampling sites of intermediate product pattern; and measuring an electrical resistance between subject sampling sites through the evaluation interconnects so as to detect a product defect in the intermediate product pattern.

Abstract: There is disclosed a memory cell which has a diffusion layers constituting source/drain areas formed on a p-type silicon substrate surface, and a channel area formed between the diffusion layers. Above the channel area, an insulating film of a laminated structure is formed of a silicon oxide film, a silicon nitride film and a silicon oxide film. A gate electrode is formed on the upper surface of the insulating film of the laminated structure. The gate electrode is used as a word line. Moreover, an interlayer insulating film is formed between the diffusion layer and the gate electrode. By injecting hot electrons from the substrate to the silicon nitride film in the insulating film of the laminated structure, data is written. The silicon nitride film and the diffusion layer are partially overlapped in a vertical direction, and an offset portion is disposed between the silicon nitride film and the diffusion layer.

Abstract: That surface portion of a semiconductor substrate which is adjacent to a buried source region formed in the substrate is covered with an offset side wall to suppress expansion of a channel beneath the offset side wall. In addition, buried source regions in the form of offset side walls are formed on the two sides of a drain region having one non-offset side wall to prevent a write or read error in unselected memory cell transistors on both sides of a selected memory transistor either in a data write or in a data read.

Abstract: Cryptographic key data and data subjected to an operation by use of the cryptographic key data are previously stored in a memory cell array. A memory cell in which the cryptographic key data is stored is accessed and latched and the cryptographic key data is latched in a latch circuit before read out data from the memory cell array. After this, the latched data and data output from a sense amplifier are subjected to an operation by an arithmetical circuit to decode the data and the result of the operation is output as readout data.

Abstract: A data transfer control circuit is connected between a sense amplifier and output buffer circuit. The data transfer control circuit is controlled by a pulse signal supplied from a pulse signal generator so as to have longer delay time which pulse signal is not generated by the pulse signal generator, and operate as noise canceller and prevents from outputting erroneous signal therefrom to the output buffer circuit.

Abstract: In a nonvolatile semiconductor memory device, a wiring layer is connected between a power source and a memory cell. Resistance of the wiring layer is larger than the on-resistance of a load transistor, so that the load transistor substantially determines the load characteristic. Therefore, the load characteristic curve is more gentle in inclination and more rectilinear in shape. This makes the data writing operation stable against a variance in the channel lengths of manufactured transistors forming the memory cells.

Abstract: A semiconductor memory device includes word lines selectively driven by a signal from a row decoder, memory cells connected to word lines, first and second data lines, a bit line connected to receive data from the memory cell and to supply received data to the first data lines, dummy cells connected to word lines, first and second dummy data lines, a dummy bit lines connected to receive data from the dummy memory cell and to supply received data to the first dummy data line, a data sensing circuit for generating an output signal corresponding to a potential difference between the second data line and second dummy data line, a first MOS transistor connected between the first and second data lines, a first load circuit for charging the second data line, a second MOS transistor connected between the first and second dummy data lines, and a second load circuit for charging the second dummy data lines.

Abstract: A data transfer control circuit is connected between a sense amplifier and output buffer circuit. The data transfer control circuit is controlled by a pulse signal supplied from a pulse signal generator so as to have longer delay time which pulse signal is not generated by the pulse signal generator, and operate as noise canceller and prevents from outputting erroneous signal therefrom to the output buffer circuit.

Abstract: In a nonvolatile semiconductor memory device, a wiring layer is connected between a power source and a memory cell. Resistance of the wiring layer is larger than the on-resistance of a load transistor, so that the load transistor substantially determines the load characteristic. Therefore, the load characteristic curve is more gentle in inclination and more rectilinear in shape. This makes the data writing operation stable against a variance in the channel lengths of manufactured transistors forming the memory cells.

Abstract: A semiconductor memory device in which data can be read out in response to an address signal comprises power source lines, a plurality of row and column conductive lines, a memory cell array including nonvolatile memory cells arranged in a matrix form of rows and columns and respectively connected to the plurality of row and column lines and the power source lines, a first selector circuit for generating a signal for selecting the row conductive lines in response to an address signal, a dummy row line, and a dummy memory cells each having a source, a drain and a control gate connected to the dummy row line.

Abstract: A data transfer control circuit is connected between a sense amplifier and output buffer circuit. The data transfer control circuit is controlled by a pulse signal supplied from a pulse signal generator so as to have longer delay time which pulse signal is not generated by the pulse signal generator, and operate as noise canceller and prevents from outputting erroneous signal therefrom to the output buffer circuit.