Abstract: According to one embodiment, a memory element includes a first conductive layer, a second conductive layer, and a first layer. The first conductive layer includes an ion source. The first layer includes a first element and is provided between the first conductive layer and the second conductive layer. An electronegativity of the first element is greater than 2. The first layer includes a first region and a second region. The first region includes the first element. The second region is provided between the first region and the second conductive layer. The second region does not include the first element, or the second region includes the first element, and a concentration of the first element in the first region is higher than a concentration of the first element in the second region.

Abstract: According to one embodiment, a memory element includes a first conductive layer, a second conductive layer, and a first layer. The first conductive layer includes an ion source. The first layer includes a first element and is provided between the first conductive layer and the second conductive layer. An electronegativity of the first element is greater than 2. The first layer includes a first region and a second region. The first region includes the first element. The second region is provided between the first region and the second conductive layer. The second region does not include the first element, or the second region includes the first element, and a concentration of the first element in the first region is higher than a concentration of the first element in the second region.

Abstract: An arithmetic control device according to an embodiment controls arithmetic operations using a memory chip. The memory chip includes a memory cell array and a controller. The memory cell array includes a plurality of memory cells. The controller is configured to control access to the memory cell array. The arithmetic control device includes a first writing unit and a first reading unit. The first writing unit requests the controller to write a first value to a second cell near a first cell of the memory cell array. The first reading unit requests the controller to read a second value from the first cell after the first value is written to the second cell.

Abstract: An individual identification device (1) according to embodiments may identify a storage device (100) including one or more memory chips (40). The device comprises a first storage (40), a region allocator (15), and a hardware fingerprint generator (12). The first storage may be configured to store write data. The region allocator may be configured to write the write data in a specific region in each memory chip. The hardware fingerprint generator may be configured to generate hardware fingerprint data based on mismatch bits between the write data and read data read out from the specific region in each memory chip.

Abstract: It is made possible to provide a method for manufacturing a semiconductor device that has a high-quality insulating film in which defects are not easily formed, and experiences less leakage current. A method for manufacturing a semiconductor device, includes: forming an amorphous silicon layer on an insulating layer; introducing oxygen into the amorphous silicon layer; and forming a silicon oxynitride layer by nitriding the amorphous silicon layer having oxygen introduced thereinto.

Abstract: According to an embodiment, a comparator includes a first transistor, a second transistor, an output stage, and a node group. The first transistor is configured to operate when a first voltage applied thereto exceeds a first threshold value, and is disposed in an input stage. The second transistor is configured to operate when a second voltage applied thereto exceeds a second threshold value and is disposed in the input stage. The output stage is configured to perform voltage switching and output according to the change in the magnitude relationship between the first voltage and the second voltage. The node group is configured to, during a non-operational state in which the first voltage and the second voltage are not compared, vary at least either the first threshold value or the second threshold value.

Abstract: According to an embodiment, a memory system includes first wiring lines; second wiring lines; third wiring lines; fourth wiring lines; and first and second storages. The first storage includes first memory cells arranged at intersections of the first wiring lines and the second wiring lines. Each of the third wiring lines is connected to any one of the first wiring lines. Each of the fourth wiring lines is pre-associated with a logical address specified by a host apparatus. The second storage includes second memory cells arranged at intersections of the third wiring lines and the fourth wiring lines. A resistance state of each of the second memory cells is set to a first resistance state or a second resistance state where a resistance value is lower than that in the first resistance state, according to a correspondence relationship between the logical address and the first wiring line.

Abstract: An arithmetic control device according to an embodiment controls arithmetic operations using a memory chip. The memory chip includes a memory cell array and a controller. The memory cell array includes a plurality of memory cells. The controller is configured to control access to the memory cell array. The arithmetic control device includes a first writing unit and a first reading unit. The first writing unit requests the controller to write a first value to a second cell near a first cell of the memory cell array. The first reading unit requests the controller to read a second value from the first cell after the first value is written to the second cell.

Abstract: According to an embodiment, a comparator includes a first transistor, a second transistor, an output stage, and a node group. The first transistor is configured to operate when a first voltage applied thereto exceeds a first threshold value, and is disposed in an input stage. The second transistor is configured to operate when a second voltage applied thereto exceeds a second threshold value and is disposed in the input stage. The output stage is configured to perform voltage switching and output according to change in magnitude relationship between the first voltage and the second voltage. The node group is configured to, during a non-operational state in which the first voltage and the second voltage are not compared, vary at least either the first threshold value or the second threshold value.

Abstract: An imaging element according to embodiments may comprise a plurality of photoreceivers (11a), a plurality of scanning circuits (11b), a first wiring (L2), a plurality of second wirings (L1), and at least one variable resistance element (VR2). The plurality of scanning circuits (11b) may be connected to the plurality of photoreceivers, respectively. Each of the second wirings (L1) may branch off from the first wiring and be connected to one of the scanning circuits. The at least one variable resistance element (VR2) may be located on the first wiring so as to electrically intervene between adjacent branching points (N1, N2) among a plurality of branching points between the first wiring and the second wirings.

Abstract: It is made possible to provide a method for manufacturing a semiconductor device that has a high-quality insulating film in which defects are not easily formed, and experiences less leakage current. A method for manufacturing a semiconductor device, includes: forming an amorphous silicon layer on an insulating layer; introducing oxygen into the amorphous silicon layer; and forming a silicon oxynitride layer by nitriding the amorphous silicon layer having oxygen introduced thereinto.

Abstract: An individual identification device (1) according to embodiments may identify a storage device (100) including one or more memory chips (40). The device comprises a first storage (40), a region allocator (15), and a hardware fingerprint generator (12). The first storage may be configured to store write data. The region allocator may be configured to write the write data in a specific region in each memory chip. The hardware fingerprint generator may be configured to generate hardware fingerprint data based on mismatch bits between the write data and read data read out from the specific region in each memory chip.

Abstract: According to an embodiment, a memory system includes first wiring lines; second wiring lines; third wiring lines; fourth wiring lines; and first and second storages. The first storage includes first memory cells arranged at intersections of the first wiring lines and the second wiring lines. Each of the third wiring lines is connected to any one of the first wiring lines. Each of the fourth wiring lines is pre-associated with a logical address specified by a host apparatus. The second storage includes second memory cells arranged at intersections of the third wiring lines and the fourth wiring lines. A resistance state of each of the second memory cells is set to a first resistance state or a second resistance state where a resistance value is lower than that in the first resistance state, according to a correspondence relationship between the logical address and the first wiring line.

Abstract: A non-volatile variable resistive element according to an embodiment comprises a first electrode including a first metal, a second electrode including a second metal, a third electrode placed opposite to the first and second electrodes, and a variable resistive layer placed between the first and second electrodes and the third electrode, a resistance of the variable resistive layer reducing when at least either one of the first metal and the second metal is diffused into the variable resistive layer and the resistance of the variable resistive layer rising when at least either one of the first metal and the second metal diffused into the variable resistive layer is collected by the first electrode or the second electrode.

Abstract: According to an embodiment, an error correction device includes first calculators, second calculators, estimators, and an inverter. Each first calculator calculates a first message representing a probability that 1-bit data that is input in a corresponding variable node is 1. Each second calculator calculates a second message representing a probability that a value of the data input to the variable node is 1 for each of two or more variable nodes connected to the check node by using the first messages of the variable nodes connected to the check node. Each estimator estimates a true value of the data input to the variable node to generate an estimated value by using the first and second messages. The inverter inverts the estimated value associated with at least one of the variable nodes with a probability higher than 0 and lower than 1.

Abstract: It is made possible to provide a method for manufacturing a semiconductor device that has a high-quality insulating film in which defects are not easily formed, and experiences less leakage current. A method for manufacturing a semiconductor device, includes: forming an amorphous silicon layer on an insulating layer; introducing oxygen into the amorphous silicon layer; and forming a silicon oxynitride layer by nitriding the amorphous silicon layer having oxygen introduced thereinto.

Abstract: It is made possible to provide a method for manufacturing a semiconductor device that has a high-quality insulating film in which defects are not easily formed, and experiences less leakage current. A method for manufacturing a semiconductor device, includes: forming an amorphous silicon layer on an insulating layer; introducing oxygen into the amorphous silicon layer; and forming a silicon oxynitride layer by nitriding the amorphous silicon layer having oxygen introduced thereinto.

Abstract: According to one embodiment, nonvolatile memory device includes a semiconductor layer, a conductive layer and a resistance change layer. The semiconductor layer has an impurity concentration less than 1×1019 cm?3. The resistance change layer is provided between the semiconductor layer and the conductive layer. The resistance change layer includes a fixed charge. The resistance change layer is reversibly transitionable between a first state and a second state by at least one selected from a current supplied via the semiconductor layer and the conductive layer and a voltage applied via the semiconductor layer and the conductive layer. A resistance of the resistance change layer in the second state is higher than a resistance of the resistance change layer in the first state.

Abstract: A non-volatile variable resistive element according to an embodiment comprises a first electrode including a first metal, a second electrode including a second metal, a third electrode placed opposite to the first and second electrodes, and a variable resistive layer placed between the first and second electrodes and the third electrode, a resistance of the variable resistive layer reducing when at least either one of the first metal and the second metal is diffused into the variable resistive layer and the resistance of the variable resistive layer rising when at least either one of the first metal and the second metal diffused into the variable resistive layer is collected by the first electrode or the second electrode.

Abstract: According to an embodiment, an error correction device includes first calculators, second calculators, estimators, and an inverter. Each first calculator calculates a first message representing a probability that 1-bit data that is input in a corresponding variable node is 1, Each second calculator calculates a second message representing a probability that a value of the data input to the variable node is 1 for each of two or more variable nodes connected to the check node by using the first, messages of the variable nodes connected to the check node. Each estimator estimates a true value of the data input to the variable node to generate an estimated value by using the first and second messages. The inverter inverts the estimated value associated with at least one of the variable nodes with a probability higher than 0 and lower than 1.