Abstract: One aspect of the invention is a terminal resistance device including a variable terminal resistance unit including a plurality of first terminal resistance elements connectable to a transmission path and a terminal resistance control unit that transmits a first control signal of a thermometer code to the variable terminal resistance unit. The first terminal resistance elements have the same resistance value and the first control signal is a signal for selecting the first terminal resistance elements to be connected to the transmission path.

Abstract: One aspect of the invention is a terminal resistance device including a variable terminal resistance unit including a plurality of first terminal resistance elements connectable to a transmission path and a terminal resistance control unit that transmits a first control signal of a thermometer code to the variable terminal resistance unit. The first terminal resistance elements have the same resistance value and the first control signal is a signal for selecting the first terminal resistance elements to be connected to the transmission path.

Abstract: A semiconductor storage device includes a circuit receiving a command signal for generating a read control signal (RPB) based on the transition of a clock signal CLK and a circuit receiving the command signal for generating a write control signal (WPB) based on the transition of the clock signal CLK. The read cycle in which decoding of an address, selection of a word line and activation of a sense amplifier are executed based on the read control signal to read cell data, and the write cycle in which decoding of an address, selection of a word line and activation of a write amplifier are executed based on the write control signal and bit line pre-charging is also carried out, are carried out alternately. The sense period of the read cycle is overlapped with the decoding period of the write cycle.

Abstract: A semiconductor storage device includes a circuit receiving a command signal for generating a read control signal (RPB) based on the transition of a clock signal CLK and a circuit receiving the command signal for generating a write control signal (WPB) based on the transition of the clock signal CLK. The read cycle in which decoding of an address, selection of a word line and activation of a sense amplifier are executed based on the read control signal to read cell data, and the write cycle in which decoding of an address, selection of a word line and activation of a write amplifier are executed based on the write control signal and bit line pre-charging is also carried out, are carried out alternately. The sense period of the read cycle is overlapped with the decoding period of the write cycle.

Abstract: A bus interface circuit includes a precharge circuit including a switch element which is inserted between a bus line and a precharge power supply, receives a precharge control signal PE at its control terminal, and is turned on when the precharge control signal is active. The precharge circuit precharges the bus line to a predetermined precharge voltage from the precharge power supply via the switch element that is turned on. The precharge voltage is a predetermined voltage between a high-potential power supply voltage VDD and a low-potential power supply voltage VSS. When a signal received by an output circuit for output to the bus line has a first logic value, an output circuit sets the bus line, which has been precharged to the precharge voltage, from the precharge voltage to the predetermined VSS.

Abstract: A bus interface circuit includes a precharge circuit including a switch element which is inserted between a bus line and a precharge power supply, receives a precharge control signal PE at its control terminal, and is turned on when the precharge control signal is active. The precharge circuit precharges the bus line to a predetermined precharge voltage from the precharge power supply via the switch element that is turned on. The precharge voltage is a predetermined voltage between a high-potential power supply voltage VDD and a low-potential power supply voltage VSS. When a signal received by an output circuit for output to the bus line has a first logic value, an output circuit sets the bus line, which has been precharged to the precharge voltage, from the precharge voltage to the predetermined VSS.

Abstract: In fuse blocks included in each of programmable circuits, an operational current of a fuse section is controlled by a current controller. In the fuse section, a diode-connected N-channel type MOS transistor is connected to an output line. In the fuse section, a diode-connected P-channel type MOS transistor is connected to an output line. A current flowing to and through the output lines is controlled by a P-channel type MOS transistor and an N-channel type MOS transistor included in the current controller.

Abstract: The output circuit of the present invention which produces an external signal at a first voltage from an internal signal at a reduced second voltage and which outputs the external signal from an output terminal, comprises: first and second MOS transistors having drains connected to the output terminal, and having gates connected to a control signal line; a third MOS transistor having a source connected to a power source of the first voltage, and having a drain connected to a source of the first MOS transistor; a fourth MOS transistor having a source connected to a ground, having a drain connected to a source of the second MOS transistor, and having a gate connected to an internal signal line; a voltage changer, which changes the voltage of the internal signal, connected to the gate of the third MOS transistor; a first capacitor connected between a gate of the first MOS transistor and a gate of the third MOS transistor; and a second capacitor connected between a gate of the second MOS transistor and a gate of

Abstract: The present invention provides a next stage buffer receiving a pair of complementary signals from a flip-flop in a latch sense amplifier circuit, wherein the next stage buffer comprises: a plurality of logic gates of the same type, each of which individually includes a series connection of at least an individual first conductivity type field effect transistor individually provided to the plurality of logic gates and a common first conductivity type field effect transistor commonly provided to the plurality of logic gates, and the common first conductivity type field effect transistor is connected to a carrier supply line which supplies carriers to the common first conductivity type field effect transistor, so that the plurality of logic gates have a common node between the first conductivity type field effect transistors and the common first conductivity type field effect transistor.

Abstract: The output circuit of the present invention which produces an external signal at a first voltage from a internal signal at a reduced second voltage and which outputs the external signal from an output terminal, comprises: first and second MOS transistors having drains connected to the output terminal, and having gates connected to a control signal line; a third MOS transistor having a source connected to a power source of the first voltage, and having a drain connected to a source of the first MOS transistor; a fourth MOS transistor having a source connected to a ground, having a drain connected to a source of the second MOS transistor, and having a gate connected to an internal signal line; a voltage changer, which changes the voltage of the internal signal, connected to the gate of the third MOS transistor; a first capacitor connected between a gate of the first MOS transistor and a gate of the third MOS transistor; and a second capacitor connected between a gate of the second MOS transistor and a gate of t

Abstract: A delay circuit having: a first delay inverter having complementarily-connected first p-channel FET and first n-channel FET, one of the first p-channel and first n-channel FETs being provided with a gate length elongated; a second delay inverter having complementarily-connected second p-channel FET and second n-channel FET, one of the second p-channel and second n-channel FETs being provided with a gate length elongated; a NAND gate having a first input to which the input signal is applied and a second input to which the output signal of the second delay inverter is applied; and an inverter to output inverting the output signal of the NAND gate.

Abstract: An SRAM of the present invention has a first load resistor connected between a first power source terminal and a first node, a second load resistor connected between the first power source terminal and a second node, a first drive transistor having a source-drain path connected between the first node and a second power source terminal, and a gate connected to the second node, a second drive transistor having a source-drain path connected between the second node and the second power source terminal, and a gate connected to the first node, a first switching transistor having a source-drain path connected between the first node and a first bit line, and a gate connected to a word line, and a second switching transistor having a source-drain path connected between the first node and a second bit line, and a gate connected to the word line.

Abstract: A motorcycle is provided with first and a second fuel tanks. These tanks are provided with fuel charging ports respectively. Both the fuel tanks are intercommunicated through a communicating pipe. Since the communicating pipe can be shut by a cock, fuel can be charged into both the tanks promptly through both the fuel charging ports. The communicating pipe is provided with a fuel pump actuated by a diaphragm communicated with an intake manifold of an engine. Accordingly, even if one of the fuel tanks is disposed at a location lower than the carburetor, fuel within the fuel tank can be fed to the carburetor via the other fuel tank. The first and the second fuel tanks may be combined to constitute a single fuel tank.