Patents by Inventor Yuuji Mizuno

Yuuji Mizuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9142573
    Abstract: Each of the auxiliary capacitors (6a) includes a capacitor line (11b) comprised of the same material as the gate electrode (11a) and provided in the same layer as the gate electrode (11a), the gate insulating film (12) provided so as to cover the capacitor line (11a), a capacitor intermediate layer (13c) provided using the oxide semiconductor and provided on the gate insulating film (12) so as to overlap the capacitor line (11b), and a capacitor electrode (15b) provided on the capacitor intermediate layer (13c), and the capacitor intermediate layer (13c) is conductive.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: September 22, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tetsuya Yamashita, Tokuo Yoshida, Yoshimasa Chikama, Yoshifumi Ohta, Yuuji Mizuno, Hinae Mizuno, Masahiko Suzuki, Okifumi Nakagawa, Yoshiyuki Harumoto, Yoshinobu Miyamoto
  • Publication number: 20130207114
    Abstract: An active matrix substrate (20a) includes a plurality of pixel electrodes (18a) arranged in a matrix, and a plurality of TFTs (5) each connected to a corresponding one of the pixel electrodes (18a), and each including a gate electrode (11a) provided on an insulating substrate (10a), a gate insulating film (12a) covering the gate electrode (11a), a semiconductor layer (16a) provided on the gate insulating film (12a) and having a channel region (C) overlapping the gate electrode (11a), and a source electrode (15aa) and a drain electrode (15b) of copper or copper alloy provided on the gate insulating film (12a) and separated from each other by the channel region (C) of the semiconductor layer (16a). The semiconductor layer (16a) is formed of an oxide semiconductor and covers the source electrode (15aa) and the drain electrode (15b).
    Type: Application
    Filed: February 14, 2011
    Publication date: August 15, 2013
    Inventors: Masahiko Suzuki, Yoshimasa Chikama, Yuuji Mizuno, Hinae Mizuno, Yoshifumi Ohta, Tokuo Yoshida, Okifumi Nakagawa, Yoshiyuki Harumoto, Yoshinobu Miyamoto, Tetsuya Yamashita
  • Publication number: 20130112970
    Abstract: A TFT substrate (30a) including a TFT (5a) having: a gate electrode (14a) provided on a substrate (10a); a gate insulating film (15) provided to cover the gate electrode (14a); a semiconductor layer (16a) made of an oxide semiconductor provided on the gate insulating film (15) with a channel region (C) arranged to lie above the gate electrode (14a): and a source electrode (19aa) and a drain electrode (19b) provided on the semiconductor layer (16a) to be spaced from each other with the channel region (C) therebetween. A recess (R) is provided on the surface of the channel region (C) of the semiconductor layer (16a) to extend in the channel width direction.
    Type: Application
    Filed: June 6, 2011
    Publication date: May 9, 2013
    Inventors: Yoshinobu Miyamoto, Okifumi Nakagawa, Yoshifumi Ohta, Yuuji Mizuno, Yoshimasa Chikama, Tokuo Yoshida, Masahiko Suzuki, Yoshiyuki Harumoto, Tetsuya Yamashita
  • Publication number: 20120241750
    Abstract: A semiconductor device includes: a thin film transistor having a gate line (3a), a first insulating film (5), an island-shaped oxide semiconductor layer (7a), a second insulating film (9), a source line (13as), a drain electrode (13ad), and a passivation film; and a terminal portion having a first connecting portion (3c) made of the same conductive film as the gate line, a second connecting portion (13c) made of the same conductive film as the source line and the drain electrode, and a third connecting portion (19c) formed on the second connecting portion.
    Type: Application
    Filed: December 3, 2010
    Publication date: September 27, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yoshimasa Chikama, Hirohiko Nishiki, Yoshifumi Ohta, Yuuji Mizuno, Hinae Mizuno, Takeshi Hara, Tetsuya Aita, Masahiko Suzuki, Michiko Takei, Okifumi Nakagawa, Yoshiyuki Harumoto
  • Publication number: 20120218485
    Abstract: An active matrix substrate includes a plurality of pixels arranged in a matrix, a plurality of capacitor lines (11b) extending in one of directions in which the pixels are aligned and in parallel to each other, a plurality of TFTs (5), one for each of the pixels, a protective film (16a) covering the TFTs (5), a plurality of pixel electrodes (18a) arranged in a matrix on the protective film (16a) and connected to the respective corresponding TFTs (5), and a plurality of auxiliary capacitors (6), one for each of the pixels. Each of the auxiliary capacitors (6) includes the corresponding capacitor line (11b), the corresponding pixel electrode (18a), and the protective film (16a) between the corresponding capacitor line (11b) and the corresponding pixel electrode (18a).
    Type: Application
    Filed: July 26, 2010
    Publication date: August 30, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yoshimasa Chikama, Hirohiko Nishiki, Yoshifumi Ohta, Yuuji Mizuno, Hinae Mizuno, Takeshi Hara, Tetsuya Aita, Masahiko Suzuki, Michiko Takei, Okifumi Nakagawa, Yoshiyuki Harumoto
  • Publication number: 20120138923
    Abstract: The present invention provides a thin film transistor including an oxide semiconductor layer (4) for electrically connecting a signal electrode (6a) and a drain electrode (7a), the an oxide semiconductor layer being made from an oxide semiconductor; and a barrier layer (6b) made from at least one selected from the group consisting of Ti, Mo, W, Nb, Ta, Cr, nitrides thereof, and alloys thereof, the barrier layer (6b) being in touch with the signal electrode (6a) and the oxide semiconductor layer (4) and separating the signal electrode (6a) from the oxide semiconductor layer (4). Because of this configuration, the thin film transistor can form and maintain an ohmic contact between the first electrode and the channel layer, thereby being a thin film transistor with good properties.
    Type: Application
    Filed: April 6, 2010
    Publication date: June 7, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Takeshi Hara, Hirohiko Nishiki, Yoshimasa Chikawa, Kazuo Nakagawa, Yoshifumi Ohta, Tetsuya Aita, Masahiko Suzuki, Okifumi Nakagawa, Yoshiyuki Miyajima, Yuuji Mizuno, Hinae Mizuno, Michiko Takei, Yoshiyuki Harumoto
  • Patent number: 6016433
    Abstract: Any oxide superconductor Josephson junction element having an oxide superconductor oriented in the c-axis direction with respect to a substrate, and a needle-like, a-axis (or b-axis) oriented oxide superconductor. Both sides of the needle-like, a-axis (or b-axis) oriented oxide superconductor are sandwiched between the c-axis oriented superconductors. The crystal boundary sections between the needle-like, a-axis (or b-axis) oriented oxide superconductor and each of the c-axis oriented superconductors form a weak link of the Josephson junction. The needle-like, a-axis (or b-axis) oriented oxide superconductor is grown such that the c-axis direction thereof is oriented in the (110) direction which is inclined at an angle of 45 degrees with respect to the (100) direction or (010) direction of the c-axis oriented superconductors.
    Type: Grant
    Filed: September 2, 1997
    Date of Patent: January 18, 2000
    Assignees: International Superconductivity Technology Center, Sharp Kabushiki Kaisha
    Inventors: Yuuji Mizuno, Yoshihiro Ishimaru, Youichi Enomoto
  • Patent number: 5877122
    Abstract: An oxide superconductor element, produced by forming a damaged region on a substrate surface by the Ga.sup.+ focusing ion beam method and then depositing an oxide superconductor thin-film over it, is characterized in that a NdBa.sub.2 Cu.sub.3 O.sub.7-y (0.ltoreq.y.ltoreq.0.5) oxide superconductor is used in a tunnel junction having a tunneling barrier region with weak superconductivity.
    Type: Grant
    Filed: May 17, 1996
    Date of Patent: March 2, 1999
    Assignees: Fujitsu Ltd., Sharp Kabushiki Kaisha, NEC Corp., International Superconductivity Technology Center
    Inventors: Yoshihiro Ishimaru, Yuuji Mizuno, Katsumi Suzuki, Youichi Enomoto, Shoji Tanaka