Abstract: For making in a parallel computer system an interconnection network transfer data sequences, each composed of consecutive packets, from input ports (17) to a destination port indicated among output ports (19) by a routing address specified by a leading packet of each data sequence, control registers (31) hold the routing address of a privileged sequence determined by arbiters (39) in response to such addresses held in the control registers and stored in control buffers (33). Data of the consecutive packets of the privileged sequence are simultaneously stored in and produced from data buffers (37). Controlled by the arbiters, input selectors (41, 43) select the data for delivery to the destination port through output buffers (55) and output selectors (57) controlled by a selector operating arrangement (59-63).

Abstract: In a multi-processor system, a priority arbitrator receives a request issued from each of processors, and arbitrates conflicts occurring among the requests. The requests derived from the respective processors are inputted via selectors to fixed priority arbitrating circuits. Only one request is selected by the fixed priority arbitrating circuit, and the selected request is held in an output register. The pending request is detected by an AND circuit, and the detection result is held in a pending register. When there is such a request held in the pending register, the subsequent request is not selected by the selector. The priorities of the plural fixed priority arbitrating circuits within the multi-processor system may be made different from each other, depending upon the use conditions of the multi-processor system.