Patents by Inventor Yuuki Fujiwara

Yuuki Fujiwara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240077813
    Abstract: A developing device includes a developer bearer rotatable in a rotation direction and forming a developing range, a holder, and an entrance seal. The holder has a facing face facing the developer bearer upstream from the developing range in the rotation direction, a support face defining a part of an outer face of the developing device, and a relay face extending from one end of the support face to one end of the relay face connected to the facing face to form an acute tip portion closer to the developing range than the one end. The entrance seal has a free end projecting from the one end as a cantilever, and a length of the entrance seal from a tip of the free end of the entrance seal to the one end is shorter than a length of the relay face from the acute tip portion to the one end.
    Type: Application
    Filed: August 21, 2023
    Publication date: March 7, 2024
    Inventors: Kei SAITO, Yoshihiro FUJIWARA, Masaki TAKAHASHI, Yuuki TSUCHIYA
  • Patent number: 7516392
    Abstract: A first run length encoder implements run length modulation of a first information signal to generate a second information signal of a run-length-limited code while subjecting the second information signal to DSV control and adding a sync signal to the second information signal to get a third information signal. A converter changes the third information signal into an NRZI signal including information code words. A parity generator produces original parity signals in response to the information code words in the NRZI signal, and combines the information code words and the original parity signals to form a first parity-added signal. A second run length encoder implements run length modulation of only the original parity signals in the first parity-added signal to convert the first parity-added signal into a second parity-added signal while subjecting the second parity-added signal to DSV control. The second parity-added signal is recorded on a recording medium.
    Type: Grant
    Filed: August 15, 2005
    Date of Patent: April 7, 2009
    Assignee: Victor Comapny of Japan, Ltd.
    Inventors: Junichiro Tonami, Yuuki Fujiwara
  • Patent number: 7423949
    Abstract: A signal of a run-length-limited code is read out from a recording medium. The read-out signal is converted into a reproduced digital signal. A decoder subjects the reproduced digital signal to first decoding different from run length decoding to get a first decoded signal. Information bit streams are generated from the first decoded signal. The information bit streams are different in timing by 1-bit-correpsonding intervals. Run length decoders subject the information bit streams to run length decoding to get run-length-decoded bit streams respectively. Each of the run-length-decoded bit streams undergoes one of error correction and error detection. A decision is made as to which of the run-length-decoded bit streams is the smallest in error number on the basis of results of the one of error correction and error detection. The run-length-decoded bit stream being the smallest in error number is selected and outputted as a likeliest information bit stream.
    Type: Grant
    Filed: August 1, 2005
    Date of Patent: September 9, 2008
    Assignee: Victor Company of Japan, Ltd.
    Inventors: Junichiro Tonami, Yuuki Fujiwara
  • Publication number: 20060123328
    Abstract: A first run length encoder implements run length modulation of a first information signal to generate a second information signal of a run-length-limited code while subjecting the second information signal to DSV control and adding a sync signal to the second information signal to get a third information signal. A converter changes the third information signal into an NRZI signal including information code words. A parity generator produces original parity signals in response to the information code words in the NRZI signal, and combines the information code words and the original parity signals to form a first parity-added signal. A second run length encoder implements run length modulation of only the original parity signals in the first parity-added signal to convert the first parity-added signal into a second parity-added signal while subjecting the second parity-added signal to DSV control. The second parity-added signal is recorded on a recording medium.
    Type: Application
    Filed: August 15, 2005
    Publication date: June 8, 2006
    Applicant: Victor Company of Japan, Ltd.
    Inventors: Junichiro Tonami, Yuuki Fujiwara
  • Publication number: 20060028749
    Abstract: A signal of a run-length-limited code is read out from a recording medium. The read-out signal is converted into a reproduced digital signal. A decoder subjects the reproduced digital signal to first decoding different from run length decoding to get a first decoded signal. Information bit streams are generated from the first decoded signal. The information bit streams are different in timing by 1-bit-correpsonding intervals. Run length decoders subject the information bit streams to run length decoding to get run-length-decoded bit streams respectively. Each of the run-length-decoded bit streams undergoes one of error correction and error detection. A decision is made as to which of the run-length-decoded bit streams is the smallest in error number on the basis of results of the one of error correction and error detection. The run-length-decoded bit stream being the smallest in error number is selected and outputted as a likeliest information bit stream.
    Type: Application
    Filed: August 1, 2005
    Publication date: February 9, 2006
    Applicant: Victor Company of Japan, Ltd.
    Inventors: Junichiro Tonami, Yuuki Fujiwara