Patents by Inventor Yuuki Kuro

Yuuki Kuro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220293551
    Abstract: A semiconductor manufacturing apparatus includes a stage capable of holding thereon an interconnection substrate. A tool presses the interconnection substrate and a semiconductor chip against each other between the tool and the stage. The tool includes a main body portion that has a holding surface holding thereon the semiconductor chip. A first protruding portion is provided along an outer edge of the holding surface and protrudes from the holding surface toward the stage. A second protruding portion is provided outside of the first protruding portion along the outer edge of the holding surface and protrudes from the holding surface toward the stage. A groove portion is provided between the first protruding portion and the second protruding portion.
    Type: Application
    Filed: August 31, 2021
    Publication date: September 15, 2022
    Applicant: Kioxia Corporation
    Inventor: Yuuki KURO
  • Patent number: 8859341
    Abstract: A semiconductor chip which is mounted on a wiring substrate and which is electrically connected to the wiring substrate is disposed in a sealing apparatus. A sealing resin material made of a thermosetting resin composition is supplied into the sealing apparatus. The sealing resin material contains a solid foreign matter having a cured product of a thermosetting resin, and includes particulates of the thermosetting resin composition pulverized with the solid foreign matter, a granulation powder of the particulates, or a preform of the particulates. The semiconductor chip is resin sealed by using the sealing resin material.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: October 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuuki Kuro, Makoto Minaminaka
  • Publication number: 20120286411
    Abstract: According to one embodiment, there is provided a semiconductor device including a wiring board, a semiconductor chip mounted on a first surface of the wiring board, first external electrodes provided on the first surface of the wiring board, second external electrodes provided on a second surface of the wiring board, and a sealing resin layer sealing the semiconductor chip together with the first external electrodes. The sealing resin layer has a recessed portion exposing a part of each of the first external electrodes. The plural semiconductor devices are stacked to form a semiconductor module with a POP structure. In this case, the first external electrodes of the lower-side semiconductor device and the second external electrodes of the upper-side semiconductor device are electrically connected.
    Type: Application
    Filed: March 16, 2012
    Publication date: November 15, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Watanabe, Takashi Imoto, Naoto Takebe, Yuuki Kuro, Yusuke Doumae, Katsunori Shibuya, Yoshimune Kodama, Yuji Karakane, Masatoshi Kawato
  • Publication number: 20100062572
    Abstract: A semiconductor chip which is mounted on a wiring substrate and which is electrically connected to the wiring substrate is disposed in a sealing apparatus. A sealing resin material made of a thermosetting resin composition is supplied into the sealing apparatus. The sealing resin material contains a solid foreign matter having a cured product of a thermosetting resin, and includes particulates of the thermosetting resin composition pulverized with the solid foreign matter, a granulation powder of the particulates, or a preform of the particulates. The semiconductor chip is resin sealed by using the sealing resin material.
    Type: Application
    Filed: September 3, 2009
    Publication date: March 11, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuuki Kuro, Makoto Minaminaka