Abstract: A clock transfer circuit receives input data synchronized with a first clock, and outputs, as output data, data synchronized with a second clock having a frequency different from that of the first clock. A write address controller is operating according to the first clock, and provides a write address to a memory. A read address controller is operating according to the second clock, and provides a read address to the memory. A cycle comparator compares the cycle of a predetermined event between the input data and the output data. Based on such a comparison result, the clock adjuster adjusts the frequency of the second clock.

Abstract: A video processor receives original video data, an original synchronization signal, and an original data valid region signal from a video signal source, supplements insufficient part of the original video data relative to a predetermined valid pixel region, and outputs new video data having the predetermined valid pixel region and a new data valid region signal indicating the predetermined valid pixel region. The video processor includes a valid position regeneration controller delaying at least one of the original video data or the original synchronization signal to match positions of color-difference signals in the original video data to positions of color-difference signals in the new video data in determining based on the original synchronization signal and the original data valid region signal that the color-difference signals in the new video data are displayed while being replaced with each other; and a controller controlling operation of the valid position regeneration controller.

Abstract: A clock transfer circuit receives input data synchronized with a first clock, and outputs, as output data, data synchronized with a second clock having a frequency different from that of the first clock. A write address controller is operating according to the first clock, and provides a write address to a memory. A read address controller is operating according to the second clock, and provides a read address to the memory. A cycle comparator compares the cycle of a predetermined event between the input data and the output data. Based on such a comparison result, the clock adjuster adjusts the frequency of the second clock.

Abstract: In a video signal processing circuit, when a 2D video signal is transferred in a 3D transfer format from a video signal source, a one side mute control section provided in an input video control section determines whether the 2D video signal is on the L side or on the R side of the 3D transfer format. During a period of the one side (e.g., the L side) that is not used by the 2D video signal, the one side mute control section replaces data loaded on the one side in the video signal source with fixed data, and sends it through an input video control section, a color space changing section and a packet loading section in this order. This stops these three circuit sections from operating unnecessarily, thereby reducing the power consumption.

Abstract: In a video signal processing device, a host CPU sets a number of parameters for a memory table at its low-load timing such as during power-up. The host CPU then enables the function of an automatic setting controller. Being notified of start of automatic setting, the automatic setting controller reads plural clock setting parameters from the memory table, and performs clock setting in a clock generation section while waiting for stabilization of PLL oscillation. The automatic setting control section then reads plural signal processing parameters from the memory table and sets the parameters in a video signal processing section. Thus, in operation of the video signal processing section and the clock generation section according to the format of the input video signal, it is possible to set a number of setting parameters in these sections while reducing the load of the host CPU, shortening the image output time.