Abstract: Portions excluding magnetic elements of a laminate film of magnetic films or the like constituting magnetic elements (1) are oxidized/nitrided or oxynitrided to be insulated by a plasma processing using a conductive mask (17), whereby a plurality of magnetic elements are separated. This laminate film comprises a magnetic element region (18) formed with magnetic elements (1) and an insulated region (19) consisting of oxides/nitrides or oxynitrides. Upper wiring such as a bit line (3) is formed later. Since the conductive mask used in forming the insulated region is made part of the upper wiring, the magnetic elements and the upper wiring can be disposed in contact with each other.

Abstract: Bit lines (51) and word lines (50) nonparallel to one other are so arranged as to cross, and a magneto-resistance element (52) serving as the storage element is arranged between a bit line and a word line at their intersection. Numeral 106 represents an upper electrode. The magneto-resistance element comprises a free magnetic layer the magnetization direction of which changes with the direction of a current flowing through the bit line at the intersection. The free magnetic layer is located close to the top face of the magneto-resistance element. The distance from the free magnetic layer to the bit line is larger than that from the free magnetic layer to the word line. The width of the word line is smaller than that of the bit line. The bit lines and the word lines are arranged at their respective predetermined repetition pitches. The repetition pitches of the bit lines are larger than those of the word lines.

Abstract: Portions excluding magnetic elements of a laminate film of magnetic films or the like constituting magnetic elements (1) are oxidized/nitrided or oxynitrided to be insulated by a plasma processing using a conductive mask (17), whereby a plurality of magnetic elements are separated. This laminate film comprises a magnetic element region (18) formed with magnetic elements (1) and an insulated region (19) consisting of oxides/nitrides or oxynitrides. Upper wiring such as a bit line (3) is formed later. Since the conductive mask used in forming the insulated region is made part of the upper wiring, the magnetic elements and the upper wiring can be disposed in contact with each other.

Abstract: A magnetic memory device includes a plurality of word lines extending into a first direction, a plurality of bit lines extending into a second direction, and a plurality of magnetic memory cells which are provided at intersections of the word lines and the bit lines. Each of the memory cells includes a ferromagnetic film. Data is written in a first one of the magnetic memory cells with a synthetic magnetic field generated by first current flowing on a specific word line associated with the first magnetic memory cell and second current flowing on a specific bit line associated with the first magnetic memory cell.

Abstract: A nonvolatile storage device and method of operation capable of preventing opens in a word line and/or bit line that may result from electromigration is disclosed. A nonvolatile storage device according to an embodiment may include a number of magnetic resistance elements provided at intersections of word lines and bit lines, a word line control circuit for selecting one word line and supplying a write current thereto in a write operation, and a bit line control circuit for selecting one bit line and supplying a write current thereto. A word line control circuit can provide a bidirectional write current to a word line.

Abstract: A nonvolatile storage device and method of operation capable of preventing opens in a word line and/or bit line that may result from electromigration is disclosed. A nonvolatile storage device according to an embodiment may include a number of magnetic resistance elements provided at intersections of word lines and bit lines, a word line control circuit for selecting one word line and supplying a write current thereto in a write operation, and a bit line control circuit for selecting one bit line and supplying a write current thereto. A word line control circuit can provide a bidirectional write current to a word line.

Abstract: A magnetic memory device includes a plurality of word lines extending into a first direction, a plurality of bit lines extending into a second direction, and a plurality of magnetic memory cells which are provided at intersections of the word lines and the bit lines. Each of the memory cells includes a ferromagnetic film. Data is written in a first one of the magnetic memory cells with a synthetic magnetic field generated by first current flowing on a specific word line associated with the first magnetic memory cell and second current flowing on a specific bit line associated with the first magnetic memory cell.

Abstract: A ferroelectric memory device includes a ferroelectric capacitance element formed through an insulating film on a semiconductor substrate. The ferroelectric capacitance element includes a lower electrode, a ferroelectric film formed on the lower electrode, and an upper electrode formed on the ferroelectric film. The upper electrode has a laminate structure which contains a conductive oxide layer of first metal which is connected with the ferroelectric film.

Abstract: In a method of forming dielectric films over a substrate, a dielectric film having two parts, each with a first dielectric property, is formed and the first part of the dielectric film is subjected to a heat treatment to cause the first part of the dielectric film to have a second dielectric property different from the first dielectric property, while maintaining the first dielectric property of the second part.

Abstract: A semiconductor device is provided, which is readily and correctly designed even when the semiconductor device is further miniaturized. This device includes a semiconductor substrate, a source region and a drain region formed to be apart from each other in the substrate, a gate insulator formed on a main surface of the substrate, and a gate electrode formed on the gate insulator. The gate insulator includes a ferroelectric region and a dielectric region located in a same level as that of the ferroelectric region. The ferroelectric region is contacted with the main surface of the substrate and the gate electrode. The dielectric region is contacted with the main surface of the substrate and the ferroelectric region. The whole bottom of the ferroelectric region is contacted with the main surface of the substrate in such a way that no overlap exists between the ferroelectric region and the dielectric region.

Abstract: A non-volatile ferroelectric memory cell includes a ferroelectric capacitor polarized in either direction representative of one of the logic levels of a data bit and a field effect transistor connected between a bit line and a ground line and having a gate electrode connected to one of the electrodes of the ferroelectric capacitor, and the polarization in the ferroelectric capacitor induces movable electric charge in the gate electrode so as to change the threshold of the field effect transistor between a high level and a low level; when the movable electric charge is undesirably leaked from the gate electrode, a data restoring circuit checks the ferroelectric capacitor to see whether the polarization is directed in one direction or the other direction, and a driving circuit makes up the movable electric charge so as to enhance the reliability of the data bit stored therein.

Abstract: A potential level is applied between both electrode of a capacitor so as to polarize a ferroelectric layer sandwiched between the electrodes, and, thereafter, the node between the capacitor and a field effect transistor is caused to enter the floating state so that a large amount of electric charge is induced in the node by virtue of both of the ferroelectric component and the paraelectric component of the capacitor.

Abstract: A semiconductor memory device is composed of a plurality of memory cells. Each memory cell is comprised of a field effect transistor formed on a semiconductor substrate, wherein said field effect transistor is composed of a gate electrode structure which is composed of a gate insulating film and a gate electrode provided thereon, and source and drain regions. The memory cell is further composed of a ferroelectric capacitor composed of a lower electrode connected to said gate electrode, an upper electrode, and a capacitive ferroelectric film disposed between said upper and lower electrodes. In this case, an area of said ferroelectric capacitor is smaller than an area of one of said gate electrode and an active region of said gate electrode such that an electric field applied to said ferroelectric film is larger than a coercive electric field of said ferroelectric film and an electric field applied to said gate insulating film is smaller than a breakdown electric field of said gate insulating film.