Patents by Inventor Yuusuke FUKUMURA
Yuusuke FUKUMURA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10713171Abstract: A computer system, comprising first computers, an application operate on each of the first computers; the each of the first computers is coupled to a second computer for providing a storage area; the each of the first computers includes a processor, a memory, a cache device to which a cache area, and a interface; the memory includes a program for realizing an operating system; the operating system includes a cache driver; and a cooperation control module configured to issue a control I/O request for instructing arrangement control; and the cooperation control module generate the control I/O request from a detected I/O request based on a analysis result of the detected I/O request in a case where an issuance of the I/O request from the cache driver is detected; and transfer the control I/O request to an apparatus different from an apparatus of a transfer destination of the detected I/O request.Type: GrantFiled: October 3, 2014Date of Patent: July 14, 2020Assignee: HITACHI, LTD.Inventors: Nobukazu Kondo, Ken Sugimoto, Yuusuke Fukumura
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Publication number: 20170308472Abstract: A computer system, comprising first computers, an application operate on each of the first computers; the each of the first computers is coupled to a second computer for providing a storage area; the each of the first computers includes a processor, a memory, a cache device to which a cache area, and a interface; the memory includes a program for realizing an operating system; the operating system includes a cache driver; and a cooperation control module configured to issue a control I/O request for instructing arrangement control; and the cooperation control module generate the control I/O request from a detected I/O request based on a analysis result of the detected I/O request in a case where an issuance of the I/O request from the cache driver is detected; and transfer the control I/O request to an apparatus different from an apparatus of a transfer destination of the detected I/O request.Type: ApplicationFiled: October 3, 2014Publication date: October 26, 2017Applicant: Hitachi, Ltd.Inventors: Nobukazu KONDO, Ken SUGIMOTO, Yuusuke FUKUMURA
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Patent number: 9699254Abstract: A computer system comprising: a server on which an application operates; and a storage system that stores data used by the application, the server including an operating system for controlling the server, the operating system including a cache driver for controlling a cache, the cache driver storing access management information for managing the number of accesses to a partial storage area of a volume provided by the storage system, and the cache driver being configured to: manage the number of accesses to the partial storage area of the volume by using the first access management information; replace the storage area to which the number of accesses is to be managed based on a predetermined replacement algorithm; and control arrangement of data in the server cache based on the first access management information.Type: GrantFiled: October 6, 2014Date of Patent: July 4, 2017Assignee: Hitachi, Ltd.Inventors: Ken Sugimoto, Yuusuke Fukumura, Nobukazu Kondo
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Patent number: 9658783Abstract: In methods connecting a memory module configured from DRAM, which is high-speed memory, and a memory module configured from flash memory which is slower than DRAM but is high-capacity memory, to a CPU memory bus, in the case of sequential reading, the busy rate of the CPU memory bus increases, and performance degradation occurs easily. In the present invention, an information processing device has a CPU, a CPU memory bus, and a primary storage device. The primary storage device has a first memory module and a second memory module. The first memory module has high-speed memory. The second memory module has memory having the same memory interface as that of the high-speed memory, high-capacity memory having a different memory interface from that of the high-speed memory, and a controller that controls same. The first memory module and second memory module are caused to be accessed by the memory interface of the high-speed memory.Type: GrantFiled: March 27, 2013Date of Patent: May 23, 2017Assignee: Hitachi, Ltd.Inventors: Satoshi Muraoka, Yutaka Uematsu, Hideki Osaka, Yuusuke Fukumura, Satoru Watanabe, Masabumi Shibata, Hiroshi Kakita, Yuichi Fukuda, Takashi Miyagawa, Michinori Naito, Hitoshi Ueno, Akio Idei, Takayuki Ono, Taishi Sumikura
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Patent number: 9635123Abstract: A computer system include a service server, a storage server and a management server, wherein the service server includes a operating system, wherein the operating system includes a cache driver, wherein the storage server manages a plurality of tiered storage areas each having an access performance different from one another, wherein the management server includes an alert setting information generation part for generating alert setting information for the service servers to transmit alert information notifying a trigger to change an arrangement of data in accordance with a state of the service, and a control information generation part for generating cache control information including a first command for controlling an arrangement of cache data on a storage cache and tier control information including a second command for controlling an arrangement of the data on the plurality of tiered storage areas.Type: GrantFiled: October 28, 2014Date of Patent: April 25, 2017Assignee: Hitachi, Ltd.Inventors: Nobukazu Kondo, Ken Sugimoto, Yuusuke Fukumura
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Patent number: 9591096Abstract: A computer system, comprising: a server on which an application providing a service runs; and a storage system for storing data, the server including a cache device in which a server cache for temporarily storing data is set up, and an operating system for controlling the server, the operating system including a cache driver for controlling the server cache, wherein the operating system is configured to hold access information storing a frequency of reading data and a frequency of writing data, and wherein the cache driver is configured to: update the access information in a case where an I/O request; analyze access characteristics of data that is a target for the I/O request based on the access information; and determine whether to store the data that is the target for the I/O request in the server cache.Type: GrantFiled: May 27, 2014Date of Patent: March 7, 2017Assignee: Hitachi, Ltd.Inventors: Nobukazu Kondo, Yuusuke Fukumura, Ken Sugimoto
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Patent number: 9569144Abstract: When DRAMs that are high-speed memories and flash memories that are lower in speed but can be larger in capacity than the DRAM are to be mounted on a DIMM, what matters in maximizing CPU memory bus throughput is the arrangement of the mounted components. The present disclosure provides a memory module (DIMM) that includes memory controllers arranged on the module surface closer to a socket terminal and DRAMs serving as high-speed memories arranged on the back surface. Nonvolatile memories as large-capacity memories are arranged on the side farther from the socket terminal.Type: GrantFiled: March 27, 2013Date of Patent: February 14, 2017Assignee: Hitachi, Ltd.Inventors: Yutaka Uematsu, Satoshi Muraoka, Hideki Osaka, Masabumi Shibata, Yuusuke Fukumura, Satoru Watanabe, Hiroshi Kakita, Akio Idei, Hitoshi Ueno, Takayuki Ono, Takashi Miyagawa, Michinori Naito, Taishi Sumikura, Yuichi Fukuda
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Patent number: 9336153Abstract: A computer system, comprising a server on which an application runs, and a storage system that stores data to be used by the application, the cache driver being configured to change, in a case of the condition of a cache area is a first cache condition in which data is readable from a cache area and writing of data into the cache area is prohibited, the condition of the cache area to a third cache condition in which reading of data from the cache area is prohibited and writing of data into the cache area is prohibited, from the first cache condition.Type: GrantFiled: July 23, 2014Date of Patent: May 10, 2016Assignee: HITACHI, LTD.Inventors: Ken Sugimoto, Yuusuke Fukumura, Nobukazu Kondo
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Patent number: 9304918Abstract: A computer system, comprising: a server; and a storage system, the server including an operating system, the storage system including a storage control part, wherein the operating system is configured to: transmit a read request for first data to the storage system in a case of receiving the read request for the first data not stored in a server cache from an application; store the first data received from the storage system into the server cache, and wherein the storage control part is configured to: read the first data from the storage cache, transmit the read first data to the server, and invalidate the first data stored in the storage cache.Type: GrantFiled: May 27, 2014Date of Patent: April 5, 2016Assignee: HITACHI, LTD.Inventors: Yuusuke Fukumura, Ken Sugimoto, Nobukazu Kondo
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Publication number: 20150355846Abstract: When DRAMs that are high-speed memories and flash memories that are lower in speed but can be larger in capacity than the DRAM are to be mounted on a DIMM, what matters in maximizing CPU memory bus throughput is the arrangement of the mounted components. The present disclosure provides a memory module (DIMM) that includes memory controllers arranged on the module surface closer to a socket terminal and DRAMs serving as high-speed memories arranged on the back surface. Nonvolatile memories as large-capacity memories are arranged on the side farther from the socket terminal.Type: ApplicationFiled: March 27, 2013Publication date: December 10, 2015Inventors: Yutaka UEMATSU, Satoshi MURAOKA, Hideki OSAKA, Masabumi SHIBATA, Yuusuke FUKUMURA, Satoru WATANABE, Hiroshi KAKITA, Akio IDEI, Hitoshi UENO, Takayuki ONO, Takashi MIYAGAWA, Michinori NAITO, Taishi SUMIKURA, Yuichi FUKUDA
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Publication number: 20150347032Abstract: In methods connecting a memory module configured from DRAM, which is high-speed memory, and a memory module configured from flash memory which is slower than DRAM but is high-capacity memory, to a CPU memory bus, in the case of sequential reading, the busy rate of the CPU memory bus increases, and performance degradation occurs easily. In the present invention, an information processing device has a CPU, a CPU memory bus, and a primary storage device. The primary storage device has a first memory module and a second memory module. The first memory module has high-speed memory. The second memory module has memory having the same memory interface as that of the high-speed memory, high-capacity memory having a different memory interface from that of the high-speed memory, and a controller that controls same. The first memory module and second memory module are caused to be accessed by the memory interface of the high-speed memory.Type: ApplicationFiled: March 27, 2013Publication date: December 3, 2015Inventors: Satoshi MURAOKA, Yutaka UEMATSU, Hideki OSAKA, Yuusuke FUKUMURA, Satoru WATANABE, Masabumi SHIBATA, Hiroshi KAKITA, Yuichi FUKUDA, Takashi MIYAGAWA, Michinori NAITO, Hitoshi UENO, Akio IDEI, Takayuki ONO, Taishi SUMIKURA
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Publication number: 20150120859Abstract: A computer system include a service server, a storage server and a management server, wherein the service server includes a operating system, wherein the operating system includes a cache driver, wherein the storage server manages a plurality of tiered storage areas each having an access performance different from one another, wherein the management server includes an alert setting information generation part for generating alert setting information for the service servers to transmit alert information notifying a trigger to change an arrangement of data in accordance with a state of the service, and a control information generation part for generating cache control information including a first command for controlling an arrangement of cache data on a storage cache and tier control information including a second command for controlling an arrangement of the data on the plurality of tiered storage areas.Type: ApplicationFiled: October 28, 2014Publication date: April 30, 2015Inventors: Nobukazu KONDO, Ken SUGIMOTO, Yuusuke FUKUMURA
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Publication number: 20150100663Abstract: A computer system comprising: a server on which an application operates; and a storage system that stores data used by the application, the server including an operating system for controlling the server, the operating system including a cache driver for controlling a cache, the cache driver storing access management information for managing the number of accesses to a partial storage area of a volume provided by the storage system, and the cache driver being configured to: manage the number of accesses to the partial storage area of the volume by using the first access management information; replace the storage area to which the number of accesses is to be managed based on a predetermined replacement algorithm; and control arrangement of data in the server cache based on the first access management information.Type: ApplicationFiled: October 6, 2014Publication date: April 9, 2015Applicant: Hitachi, Ltd.Inventors: KEN SUGIMOTO, Yuusuke FUKUMURA, Nobukazu KONDO
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Publication number: 20150032965Abstract: A computer system, comprising a server on which an application runs, and a storage system that stores data to be used by the application, the cache driver being configured to change, in a case of the condition of a cache area is a first cache condition in which data is readable from a cache area and writing of data into the cache area is prohibited, the condition of the cache area to a third cache condition in which reading of data from the cache area is prohibited and writing of data into the cache area is prohibited, from the first cache condition.Type: ApplicationFiled: July 23, 2014Publication date: January 29, 2015Inventors: Ken SUGIMOTO, Yuusuke FUKUMURA, Nobukazu KONDO
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Publication number: 20140359063Abstract: A computer system, comprising: a server on which an application providing a service runs; and a storage system for storing data, the server including a cache device in which a server cache for temporarily storing data is set up, and an operating system for controlling the server, the operating system including a cache driver for controlling the server cache, wherein the operating system is configured to hold access information storing a frequency of reading data and a frequency of writing data, and wherein the cache driver is configured to: update the access information in a case where an I/O request; analyze access characteristics of data that is a target for the I/O request based on the access information; and determine whether to store the data that is the target for the I/O request in the server cache.Type: ApplicationFiled: May 27, 2014Publication date: December 4, 2014Applicant: HITACHI, LTD.Inventors: Nobukazu KONDO, Yuusuke FUKUMURA, Ken SUGIMOTO
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Publication number: 20140359227Abstract: A computer system, comprising: a server; and a storage system, the server including an operating system, the storage system including a storage control part, wherein the operating system is configured to: transmit a read request for first data to the storage system in a case of receiving the read request for the first data not stored in a server cache from an application; store the first data received from the storage system into the server cache, and wherein the storage control part is configured to: read the first data from the storage cache, transmit the read first data to the server, and invalidate the first data stored in the storage cache.Type: ApplicationFiled: May 27, 2014Publication date: December 4, 2014Applicant: HITACHI, LTD.Inventors: Yuusuke FUKUMURA, Ken SUGIMOTO, Nobukazu KONDO