Abstract: A microprocessor capable of executing a micro-instruction output from a micro-memory according to an address which corresponds to an instruction to be executed at a time when each time the microprocessor receives the address is provided. The microprocessor includes a unit (a T1 cycle signal generator, a T2 cycle signal generator, a TW cycle signal generator) for generating a control signal for a period of time corresponding to a period of time of a waiting signal at a time when the waiting signal is received from the outside, and a unit (a microcode read-only memory, a read-only memory address latch, a read-only memory output latch, an address control circuit, a multiplexer) connected to the control signal generating unit (the T1 cycle signal generator, the T2 cycle signal generator, the TW cycle signal generator) for holding an address supplied to the micro-memory for a period of time corresponding to a period of time of the control signal.