Abstract: According to one embodiment, a memory system includes a memory chip and a controller coupled to the memory chip and configured to: instruct the memory chip to execute a write operation in one of a first operation mode and a second operation mode, a program voltage used in the second operation mode being determined on the basis of first information obtained in the first operation mode; manage a power consumption value of the second operation mode on the basis of the first information; and perform power throttling control on the basis of the managed power consumption value.

Abstract: A memory system includes a memory controller comprising n (where n>2) first data input/output terminals, a first semiconductor chip comprising n second data input/output terminals, each of the second data input/output terminals being connected to a respective one of the first data input/output terminals, and a second semiconductor chip comprising n third data input/output terminals, each of the third data input/output terminals being connected to a respective one of the first data input/output terminals. When a first request signal is output from the memory controller, status data of the first semiconductor chip is output from a first of the second data input/output terminals that is connected to a first of the first data input/output terminals, and status data of the second semiconductor chip is output from a second of the third data input/output terminals that is connected to a second of the first data input/output terminals.

Abstract: According to one embodiment, a memory system includes a memory chip and a controller coupled to the memory chip and configured to: instruct the memory chip to execute a write operation in one of a first operation mode and a second operation mode, a program voltage used in the second operation mode being determined on the basis of first information obtained in the first operation mode; manage a power consumption value of the second operation mode on the basis of the first information; and perform power throttling control on the basis of the managed power consumption value.

Abstract: A memory device includes a nonvolatile memory unit and a memory controller. The memory controller is configured to generate a plurality of commands in accordance with requests received from a host and store the commands in a buffer, set a priority level to each of the commands based on contents thereof, and transfer the commands having a first priority level from the buffer to the nonvolatile memory unit during a first time period, and the commands having a second priority level lower than the first priority level from the buffer to the nonvolatile memory unit during a second time period. The first time period and the second time period are fixed recurring time periods, and the second time period begins after expiration of the first time period.

Abstract: A memory device includes a nonvolatile memory unit and a memory controller. The memory controller is configured to generate a plurality of commands in accordance with requests received from a host and store the commands in a buffer, set a priority level to each of the commands based on contents thereof, and transfer the commands having a first priority level from the buffer to the nonvolatile memory unit during a first time period, and the commands having a second priority level lower than the first priority level from the buffer to the nonvolatile memory unit during a second time period. The first time period and the second time period are fixed recurring time periods, and the second time period begins after expiration of the first time period.

Abstract: A memory system includes a memory controller comprising n (where n>2) first data input/output terminals, a first semiconductor chip comprising n second data input/output terminals, each of the second data input/output terminals being connected to a respective one of the first data input/output terminals, and a second semiconductor chip comprising n third data input/output terminals, each of the third data input/output terminals being connected to a respective one of the first data input/output terminals. When a first request signal is output from the memory controller, status data of the first semiconductor chip is output from a first of the second data input/output terminals that is connected to a first of the first data input/output terminals, and status data of the second semiconductor chip is output from a second of the third data input/output terminals that is connected to a second of the first data input/output terminals.

Abstract: According to one embodiment, descriptors with respective identifiers are created for a video stream and time information including its transfer start time, and the descriptors, time information, and video stream are recorded in a storage unit. In the case where a descriptor that indicates time information is read when the descriptors are successively read from the storage unit and the video stream is transferred from the storage unit to a transfer subject, transfer of the video stream is controlled on the basis of the time information.

Abstract: There is provided an electronic circuit capable of operating in a normal-operating mode and a power-saving mode. The electronic circuit includes a buffer cell having a buffer and an active pull-up unit, and a control circuit configured to invalidate the active pull-up unit and an input signal to the buffer when the electronic circuit has been switched to the power-saving mode.