Patents by Inventor Yuusuke Yamaoka

Yuusuke Yamaoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9232160
    Abstract: A voltage generation circuit includes a control circuit which outputs a first digital signal, a DAC which outputs a first analog signal corresponding to the first digital signal, and an attenuator which is connected to an output terminal of the DAC and is configured to output a voltage signal obtained by attenuating the first analog signal input from the DAC.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: January 5, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Makoto Ikuma, Hiroshi Fujinaka, Masahiro Higuchi, Yuusuke Yamaoka
  • Patent number: 9209750
    Abstract: A harmonic rejection mixer is disclosed that is capable of supporting wideband reception without any increase in circuit area. In this apparatus, transistors convert an RF signal to currents. Transistors perform frequency conversion based on the currents from the transistors and local oscillation signals. Transistors distribute the currents from the transistors to all transistors or some transistors based on a predetermined ratio. A load adds up the currents from the transistors and converts the resultant current to a voltage.
    Type: Grant
    Filed: December 25, 2013
    Date of Patent: December 8, 2015
    Assignee: PANASONIC CORPORATION
    Inventors: Masahiro Kumagawa, Yuusuke Yamaoka
  • Patent number: 9166614
    Abstract: The ramp-signal generator circuit includes a reference voltage generator that changes the voltage of a reference signal Vr to a comparator setting voltage VR for compensating for a voltage difference between a reference signal Vr and an analog input signal (Vs1-Vsn) before comparison by an analog-to-digital converter circuit and outputs a ramp signal whose slope starts from the comparator setting voltage VR in response to a start of the comparison. The ramp-signal generator circuit is configured to add a predetermined enhanced voltage VA to the comparator setting voltage VR before the comparison.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: October 20, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masahiro Higuchi, Kazuko Nishimura, Yuusuke Yamaoka, Yutaka Abe, Hiroshi Fujinaka
  • Publication number: 20150084683
    Abstract: A harmonic rejection mixer is disclosed that is capable of supporting wideband reception without any increase in circuit area. In this apparatus, transistors convert an RF signal to currents. Transistors perform frequency conversion based on the currents from the transistors and local oscillation signals. Transistors distribute the currents from the transistors to all transistors or some transistors based on a predetermined ratio. A load adds up the currents from the transistors and converts the resultant current to a voltage.
    Type: Application
    Filed: December 25, 2013
    Publication date: March 26, 2015
    Inventors: Masahiro Kumagawa, Yuusuke Yamaoka
  • Publication number: 20140036124
    Abstract: The ramp-signal generator circuit includes a reference voltage generator that changes the voltage of a reference signal Vr to a comparator setting voltage VR for compensating for a voltage difference between a reference signal Vr and an analog input signal (Vs1-Vsn) before comparison by an analog-to-digital converter circuit and outputs a ramp signal whose slope starts from the comparator setting voltage VR in response to a start of the comparison. The ramp-signal generator circuit is configured to add a predetermined enhanced voltage VA to the comparator setting voltage VR before the comparison.
    Type: Application
    Filed: October 14, 2013
    Publication date: February 6, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Masahiro HIGUCHI, Kazuko NISHIMURA, Yuusuke YAMAOKA, Yutaka ABE, Hiroshi FUJINAKA
  • Publication number: 20140034812
    Abstract: A voltage generation circuit includes a control circuit which outputs a first digital signal, a DAC which outputs a first analog signal corresponding to the first digital signal, and an attenuator which is connected to an output terminal of the DAC and is configured to output a voltage signal obtained by attenuating the first analog signal input from the DAC.
    Type: Application
    Filed: October 14, 2013
    Publication date: February 6, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Makoto IKUMA, Hiroshi FUJINAKA, Masahiro HIGUCHI, Yuusuke YAMAOKA
  • Patent number: 8188903
    Abstract: A ramp wave output circuit includes a ramp wave generation circuit generating a ramp wave, and a low-pass filter having a variable cutoff frequency, which receives the ramp wave. The low-pass filter operates at a first cutoff frequency for a predetermined time period after the receipt of the ramp wave, and at a second cutoff frequency, which is larger than the first cutoff frequency, after the predetermined time period has passed.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: May 29, 2012
    Assignee: Panasonic Corporation
    Inventors: Yuusuke Yamaoka, Hiroshi Kimura, Masahiro Higuchi
  • Patent number: 8093543
    Abstract: A resistor-ladder voltage generator circuit is provided, which controls so that k switches among consecutive (k+1) switches out of a plurality of switches connected to the resistor ladder circuit are simultaneously set to an ON state, and which temporally switches the value of k. This allows voltage waveforms having different slopes to be arbitrarily obtained, ranging from a voltage waveform having a small slope to a voltage waveform having a large slope, thereby improving the resolution of a generated voltage waveform without increasing the numbers of resistors and switches, while A/D conversion time is not increased even if the number of bits is increased. In addition, by using this voltage generator circuit as a ramp generator circuit, and by dynamically switching the slope of the ramp wave, acceleration of an image sensor is achieved.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: January 10, 2012
    Assignee: Panasonic Corporation
    Inventors: Yuusuke Yamaoka, Kazuko Nishimura
  • Publication number: 20110114827
    Abstract: A resistor-ladder voltage generator circuit is provided, which controls so that k switches among consecutive (k+1) switches out of a plurality of switches connected to the resistor ladder circuit are simultaneously set to an ON state, and which temporally switches the value of k. This allows voltage waveforms having different slopes to be arbitrarily obtained, ranging from a voltage waveform having a small slope to a voltage waveform having a large slope, thereby improving the resolution of a generated voltage waveform without increasing the numbers of resistors and switches, while A/D conversion time is not increased even if the number of bits is increased. In addition, by using this voltage generator circuit as a ramp generator circuit, and by dynamically switching the slope of the ramp wave, acceleration of an image sensor is achieved.
    Type: Application
    Filed: January 24, 2011
    Publication date: May 19, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Yuusuke YAMAOKA, Kazuko Nishimura
  • Publication number: 20100271248
    Abstract: A ramp wave output circuit includes a ramp wave generation circuit generating a ramp wave, and a low-pass filter having a variable cutoff frequency, which receives the ramp wave. The low-pass filter operates at a first cutoff frequency for a predetermined time period after the receipt of the ramp wave, and at a second cutoff frequency, which is larger than the first cutoff frequency, after the predetermined time period has passed.
    Type: Application
    Filed: November 25, 2008
    Publication date: October 28, 2010
    Inventors: Yuusuke Yamaoka, Hiroshi Kimura, Masahiro Higuchi
  • Patent number: 7767953
    Abstract: A ladder resistor circuit generates a plurality of different reference voltages. A plurality of switching circuits correspond to a plurality of taps of the ladder resistor circuit. Each of the plurality of switching circuits is connected at one end to a corresponding one of the taps and connected at the other end to an output node, and has a variable on-resistance value. A control circuit selects continuous n (where n is any integer equal to or greater than 2) of the plurality of switching circuits, turns the n switching circuits on, and sets the respective on-resistance values of the n switching circuits.
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: August 3, 2010
    Assignee: Panasonic Corporation
    Inventor: Yuusuke Yamaoka
  • Patent number: 7639997
    Abstract: The communication performance of a radio communication system is improved while keeping short time necessary for attaining synchronization. A low noise amplifier is selectively provided with one of an input signal supplied from the outside of the system and an oscillation output signal of a local oscillator. A mixer integrates the oscillation output signal of the local oscillator and an output signal of the low noise amplifier. An intensity discriminating unit discriminates the signal intensity of an output of the mixer. In a first state, the low noise amplifier amplifies the oscillation output signal of the local oscillator, and a control unit learns a frequency band of the low noise amplifier for maximizing the signal intensity on the basis of the discrimination result of the intensity discriminating unit. In a second state, the low noise amplifier is set to the frequency band learned in the first state and amplifies the input signal.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: December 29, 2009
    Assignee: Panasonic Corporation
    Inventors: Manabu Watanabe, Yuusuke Yamaoka
  • Publication number: 20080296473
    Abstract: A ladder resistor circuit generates a plurality of different reference voltages. A plurality of switching circuits correspond to a plurality of taps of the ladder resistor circuit. Each of the plurality of switching circuits is connected at one end to a corresponding one of the taps and connected at the other end to an output node, and has a variable on-resistance value. A control circuit selects continuous n (where n is any integer equal to or greater than 2) of the plurality of switching circuits, turns the n switching circuits on, and sets the respective on-resistance values of the n switching circuits.
    Type: Application
    Filed: May 2, 2008
    Publication date: December 4, 2008
    Inventor: Yuusuke YAMAOKA
  • Patent number: 7304595
    Abstract: A capacitor having a capacitance value corresponding to the size of an output current generating transistor is connected between the gate terminal of the output current generating transistor and the input terminal of an inverter circuit.
    Type: Grant
    Filed: July 24, 2006
    Date of Patent: December 4, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Yuusuke Yamaoka
  • Publication number: 20070207764
    Abstract: The communication performance of a radio communication system is improved while keeping short time necessary for attaining synchronization. A low noise amplifier is selectively provided with one of an input signal supplied from the outside of the system and an oscillation output signal of a local oscillator. A mixer integrates the oscillation output signal of the local oscillator and an output signal of the low noise amplifier. An intensity discriminating unit discriminates the signal intensity of an output of the mixer. In a first state, the low noise amplifier amplifies the oscillation output signal of the local oscillator, and a control unit learns a frequency band of the low noise amplifier for maximizing the signal intensity on the basis of the discrimination result of the intensity discriminating unit. In a second state, the low noise amplifier is set to the frequency band learned in the first state and amplifies the input signal.
    Type: Application
    Filed: March 1, 2007
    Publication date: September 6, 2007
    Inventors: Manabu Watanabe, Yuusuke Yamaoka
  • Publication number: 20070057831
    Abstract: A capacitor having a capacitance value corresponding to the size of an output current generating transistor is connected between the gate terminal of the output current generating transistor and the input terminal of an inverter circuit.
    Type: Application
    Filed: July 24, 2006
    Publication date: March 15, 2007
    Inventor: Yuusuke Yamaoka