Abstract: An image processing device and an amount-of-characteristic detecting method. The image processing apparatus includes a first image processing device to process an invisible image of an object, a second image processing device to process a visible image of the object, and a controller to control the first image processing device and the second image processing device. The first image processing device includes a first skew detector to detect a skew of the object from the invisible image of the object. The second image processing device includes a second skew detector to detect the skew from the visible image of the object, and circuitry to adjust the skew of the object based on a first result of skew detection performed by the first skew detector of the first image processing device or a second result of skew detection performed by the second skew detector of the second image processing device.

Abstract: An image processing device and an amount-of-characteristic detecting method. The image processing apparatus includes a first image processing device to process an invisible image of an object, a second image processing device to process a visible image of the object, and a controller to control the first image processing device and the second image processing device. The first image processing device includes a first skew detector to detect a skew of the object from the invisible image of the object. The second image processing device includes a second skew detector to detect the skew from the visible image of the object, and circuitry to adjust the skew of the object based on a first result of skew detection performed by the first skew detector of the first image processing device or a second result of skew detection performed by the second skew detector of the second image processing device.

Abstract: A network control device includes first and second interfaces, a first memory, a packet converter, a first data transfer section, a filter, and a packet transmission controller. The converter converts a second type of packets of a second system in the memory into a first type of packets of a first system. The filter extracts a valid first type of packets from the first type of packets read from the memory by the transfer section. In an energy saving state, the controller generates and transmits a first type of packets for transmission of the first system to the first interface when the extracted valid first type of packets are of the first type of packets, and generates and transmits a second type of packets for transmission of the second system to the second interface when the extracted valid first type of packets are of the second type of packets.

Abstract: A network control device includes first and second interfaces, a first memory, a packet converter, a first data transfer section, a filter, and a packet transmission controller. The converter converts a second type of packets of a second system in the memory into a first type of packets of a first system. The filter extracts a valid first type of packets from the first type of packets read from the memory by the transfer section. In an energy saving state, the controller generates and transmits a first type of packets for transmission of the first system to the first interface when the extracted valid first type of packets are of the first type of packets, and generates and transmits a second type of packets for transmission of the second system to the second interface when the extracted valid first type of packets are of the second type of packets.

Abstract: Control circuitry includes a converter and an arbitration unit. The converter is configured to convert a first signal based on a first communication standard to an internal second signal based on a second communication standard and output the internal second signal. The arbitration unit is configured to arbitrate between access of the internal second signal output from the converter and access of an external second signal, which is also based on the second communication standard, input from outside the control circuitry.

Abstract: Control circuitry includes a converter and an arbitration unit. The converter is configured to convert a first signal based on a first communication standard to an internal second signal based on a second communication standard and output the internal second signal. The arbitration unit is configured to arbitrate between access of the internal second signal output from the converter and access of an external second signal, which is also based on the second communication standard, input from outside the control circuitry.

Abstract: A data transfer device includes circuitry to: set information regarding a virtual channel of a counterpart device to which data are to be transferred from the data transfer device, switch between a first communication process and a second communication process according to the information regarding the virtual channel of the counterpart device, the first communication process causing the circuitry to transmit or receive the data using a single virtual channel, and the second communication process causing the circuitry to transmit or receive the data using multiple virtual channels.

Abstract: An image processing device includes an external memory interface to write image data to an image memory, and an inclination correction circuit. The inclination correction circuit generates coordinate information based on inclination information, detects, from the coordinate information, a minimum sub-scanning coordinate in each of divided areas of the image data, generates first read addresses for reading the divided areas of the image data from the image memory based on the minimum sub-scanning coordinate, reads the divided areas of the image data from the image memory based on the first read addresses, writes the divided areas of the image data to an internal memory, generates second read addresses for reading the divided areas of the image data from the internal memory based on the coordinate information, and reads the divided areas of the image data from the internal memory based on the second read addresses.

Abstract: A data transfer device includes circuitry to: set information regarding a virtual channel of a counterpart device to which data are to be transferred from the data transfer device, switch between a first communication process and a second communication process according to the information regarding the virtual channel of the counterpart device, the first communication process causing the circuitry to transmit or receive the data using a single virtual channel, and the second communication process causing the circuitry to transmit or receive the data using multiple virtual channels.

Abstract: An image processing device includes a writing circuit to write image data to a first memory, a second memory with a capacity of lines, a coordinate generating circuit to generate coordinate information based on inclination information, a deviation calculating circuit to calculate a maximum deviation amount of the image data from the coordinate information, a division number calculating circuit to calculate a division number based on the number of the lines and the deviation amount, an address generating circuit to generate an address for reading each of divided areas of the image data from the first memory, a burst length calculating circuit to calculate a burst length based on the division number and a main scanning width of the image data, and a transferring circuit to read and burst-transfer the image data from the first memory to the second memory based on the address and the burst length.

Abstract: An image processing device includes a writing circuit to write image data to an image memory and detect a write line number, a coordinate generating circuit to generate coordinate information based on inclination information, detect a minimum sub-scanning coordinate in each of divided areas of the image data, and generate first read addresses for reading the divided areas from the image memory, a reading circuit to read the divided areas from the image memory and detect a read line number, a reading control circuit to bring the reading circuit into a standby state and cancel the standby state, and a memory control circuit to generate write addresses for writing the divided areas to a memory, sequentially write the read divided areas to the memory, generate second read addresses for reading the divided areas from the memory, and sequentially read the divided areas from the memory.

Abstract: An image processing device includes a writing circuit to write image data to a first memory, a second memory with a capacity of lines, a coordinate generating circuit to generate coordinate information based on inclination information, a deviation calculating circuit to calculate a maximum deviation amount of the image data from the coordinate information, a division number calculating circuit to calculate a division number based on the number of the lines and the deviation amount, an address generating circuit to generate an address for reading each of divided areas of the image data from the first memory, a burst length calculating circuit to calculate a burst length based on the division number and a main scanning width of the image data, and a transferring circuit to read and burst-transfer the image data from the first memory to the second memory based on the address and the burst length.

Abstract: An image processing device includes an external memory interface to write image data to an image memory, and an inclination correction circuit. The inclination correction circuit generates coordinate information based on inclination information, detects, from the coordinate information, a minimum sub-scanning coordinate in each of divided areas of the image data, generates first read addresses for reading the divided areas of the image data from the image memory based on the minimum sub-scanning coordinate, reads the divided areas of the image data from the image memory based on the first read addresses, writes the divided areas of the image data to an internal memory, generates second read addresses for reading the divided areas of the image data from the internal memory based on the coordinate information, and reads the divided areas of the image data from the internal memory based on the second read addresses.

Abstract: An image processing device includes a writing circuit to write image data to an image memory and detect a write line number, a coordinate generating circuit to generate coordinate information based on inclination information, detect a minimum sub-scanning coordinate in each of divided areas of the image data, and generate first read addresses for reading the divided areas from the image memory, a reading circuit to read the divided areas from the image memory and detect a read line number, a reading control circuit to bring the reading circuit into a standby state and cancel the standby state, and a memory control circuit to generate write addresses for writing the divided areas to a memory, sequentially write the read divided areas to the memory, generate second read addresses for reading the divided areas from the memory, and sequentially read the divided areas from the memory.