Abstract: Systems and methods are provided for tracking a progress of design of a semiconductor device. In one embodiment, a method comprises receiving identification information identifying a set of tests for verification of a design under test (OUT) and generating a verification environment based on the identification information. The method further comprises generating hardware verification language coverage code corresponding to the verification environment, the hardware verification language code specifying steps for performance of the set of tests in the verification environment and generating a request for execution of the hardware verification language code. The method further comprises receiving coverage results verification information reporting results of execution of performance of the set of tests, storing the results in a database, and analyzing the results.

Abstract: Systems and methods are provided for tracking progress of design of a semiconductor device. In one embodiment, a method may comprise receiving identification information identifying a set of tests for verification of the design under test (DUT) and generating a verification environment based on the information. The method further comprises generating hardware verification language coverage code corresponding to the verification environment, the hardware verification language code specifying steps for performance of the tests in the verification environment and generating a request for execution of the hardware verification language code. The method further comprises receiving coverage results verification information reporting execution results of performance of the tests, storing the results in a database, and analyzing the results. The method also comprises identifying a verification hole, and generating a request to modify the test set in the verification environment, based on the verification hole.