Abstract: Methods and apparatus relating to a dynamic inclusive and non-inclusive caching policy are described. In an embodiment, a first cache has a higher level than a second cache. Circuitry determines a caching policy between the first cache and the second cache based on a comparison of a number of active processor cores and a threshold value. The caching policy is one of an inclusive caching policy or a non-inclusive caching policy. Other embodiments are also disclosed and claimed.

Abstract: A processor to perform an out-of-order (OOO) processing in which a reservation station (RS) may generate and process a dependency controlled flow comprising multiple micro-operations (uops) with specific clock based dispatch scheme. The RS may either combine two or more uops into a single RS entry or make a direct connection between two or more RS entries. The RS may allow more than two source values to be associated with a single RS by combining sources from the two or more uops. One or more execution units may be provisioned to perform the function defined by the uops. The execution units may receive more than two sources at a given time point and produce two or more results on different ports.

Abstract: A method and apparatus for a two micro-operation flow using source override. In one embodiment, the method includes the identification of a macro-instruction having one or more streaming single instruction multiple data extension type operands. Once received, the macro-instruction is decoded into a first micro-operation (uOP) and a second uOP. Once decoded, a signal is asserted to disable source operand override logic if the first micro-operation updates a logical destination register that matches a logical source register of the micro-operation. Otherwise, the mutual source override is active and executed by a register alias table (RAT) when uOP with matching logic source and destination register are detected in a same clock cycle. In doing so, macro-instructions having 128-bit operands may be processed using, for example, two uOPs (one for the lower half and one for the upper half) in a 64-bit implementation, while preserving the atomicity of the original instruction.

Abstract: Some embodiments of the invention provide devices, systems and methods of handling FXCH instructions data validity. For example, an apparatus in accordance with an embodiment of the invention includes a real register file unit able to perform a floating point exchange micro-instruction, by modifying an operand of a floating point micro-instruction that attempts to access a floating point register of said real register file unit, if said operand requires modification based on the floating point exchange micro-instruction.

Abstract: Two or more pointers, each of which indicates where values of a respective group of bits of a source of a particular micro-operation will be found when the particular micro-operation is executed, may not all point to the same register. Renaming of the source of the particular micro-operation may be enabled by generating one or more new micro-operations that merge the values into a single register. The one or more new micro-operations are inserted into a sequence of micro-operations that includes the particular micro-operation. Once the source of the particular micro-operation has been renamed, subsequent micro-operations in the sequence may be renamed, if appropriate, and executed, without having to wait for the values to be calculated.

Abstract: An out-of-order subsystem of a processor includes a register alias table and allocation (RAT/ALLOC) unit, a reservation station (RS) and a reorder buffer (ROB). Destination identifiers of one or more execution results that are not yet stored in any register file of the ROB may be compared to source identifiers of operands of micro-operations that are being issued to the RS. Each execution result corresponding to a destination identifier that matches one of the source identifiers is retrieved from a data path external to the ROB and routed to an appropriate port of the RS for an operand corresponding to the source identifier so that the RAT/ALLOC unit does not need to allocate a read port of the ROB for the RS to read the execution result.

Abstract: In some embodiments of the present invention, one or more elements of a processor core may receive a signal indicating that operands of a micro-instruction are narrow, for example less than or equal to 32 bits. In response to this signal, one or more components of a processor core element that are able to handle more than 32 bits of data (e.g. operands or results) may function as though they handle only 32 bits of data.

Abstract: A method and apparatus for a two micro-operation flow using source override. In one embodiment, the method includes the identification of a macro-instruction having one or more streaming single instruction multiple data extension type operands. Once received, the macro-instruction is decoded into a first micro-operation (uOP) and a second uOP. Once decoded, a signal is asserted to disable source operand override logic if the first micro-operation updates a logical destination register that matches a logical source register of the micro-operation. Otherwise, the mutual source override is active and executed by a register alias table (RAT) when uOP with matching logic source and destination register are detected in a same clock cycle. In doing so, macro-instructions having 128-bit operands may be processed using, for example, two uOPs (one for the lower half and one for the upper half) in a 64-bit implementation, while preserving the atomicity of the original instruction.

Abstract: Two or more pointers, each of which indicates where values of a respective group of bits of a source of a particular micro-operation will be found when the particular micro-operation is executed, may not all point to the same register. Renaming of the source of the particular micro-operation may be enabled by generating one or more new micro-operations that merge the values into a single register. The one or more new micro-operations are inserted into a sequence of micro-operations that includes the particular micro-operation. Once the source of the particular micro-operation has been renamed, subsequent micro-operations in the sequence may be renamed, if appropriate, and executed, without having to wait for the values to be calculated.

Abstract: In some embodiments of the present invention, one or more elements of a processor core may receive a signal indicating that operands of a micro-instruction are narrow, for example less than or equal to 32 bits. In response to this signal, one or more components of a processor core element that are able to handle more than 32 bits of data (e.g. operands or results) may function as though they handle only 32 bits of data.