Abstract: A system and method for training base classifiers in a boosting algorithm includes optimally training base classifiers considering an unreliability model, and then using a scheme with an aggregator decoder that reverse-flips inputs using inter-classifier redundancy introduced in training.

Abstract: A system and method for training base classifiers in a boosting algorithm includes optimally training base classifiers considering an unreliability model, and then using a scheme with an aggregator decoder that reverse-flips inputs using inter-classifier redundancy introduced in training.

Abstract: A system and method for allocating computational resources includes a plurality of classifiers, a memory array, and a memory controller to allocate memory from the memory array to each of the plurality of classifier. The system and method also include an optimization processor to determine an optimized bit precision value for at least one of the plurality of classifiers based upon a relative importance of the plurality of classifiers. The memory controller allocates the memory from the memory array to the plurality of classifiers based upon the determined optimized bit precision value.

Abstract: An apparatus is provided that includes a memory device including a plurality of sub-arrays, and a memory controller. The memory controller is configured to determine a value of a parameter of a corresponding write pulse for each bit of a word based on a relative importance of each bit, and write each bit of the word to a corresponding one of the plurality of sub-arrays using the corresponding write pulses.

Abstract: Modifying a page stored in a non-volatile storage includes receiving one or more requests to modify data stored in the page with new data. One or more lines are identified in the page that include data to be modified by the one or more requests. The identified one or more lines correspond to one or more respective byte ranges each of a predetermined size in the page. Encoded data is created based on the new data and respective locations of the one or more identified lines in the page. The encoded data is cached, and at least a portion of the cached encoded data is used to rewrite the page in the non-volatile storage to include at least a portion of the new data.

Abstract: Modifying a page stored in a non-volatile storage includes receiving one or more requests to modify data stored in the page with new data. One or more lines are identified in the page that include data to be modified by the one or more requests. The identified one or more lines correspond to one or more respective byte ranges each of a predetermined size in the page. Encoded data is created based on the new data and respective locations of the one or more identified lines in the page. The encoded data is cached, and at least a portion of the cached encoded data is used to rewrite the page in the non-volatile storage to include at least a portion of the new data.

Abstract: An apparatus is provided that includes a memory device including a plurality of sub-arrays, and a memory controller. The memory controller is configured to determine a value of a parameter of a corresponding write pulse for each bit of a word based on a relative importance of each bit, and write each bit of the word to a corresponding one of the plurality of sub-arrays using the corresponding write pulses.

Abstract: A system and method include determining, by a memory controller associated with a memory device, a value of a parameter of a write pulse for a plurality of bits of a B-bit word to be stored in the memory device. The value of the parameter is based upon a relative importance of a bit position of the plurality of bits in the B-bit word to a performance of a machine learning or signal processing task involving the B-bit word, a fidelity metric, and a resource metric. The system and method also include writing each of the plurality of bits of the B-bit word in a different sub-array of the memory device using the write pulse generated based on the value of the parameter determined for a particular one of the plurality of bits.

Abstract: A system and method for refreshing memory cells of a memory device includes storing each bit of a B-bit word in a different sub-array of a memory device. Each of the bits is associated with a bit position, and the memory device includes a plurality of sub-arrays. The system and method also include determining a refresh interval for a plurality of the bit positions based upon a relative importance of the plurality of the bit positions to a performance of a machine learning or signal processing task involving the B-bit word. The refresh interval is based upon a fidelity metric and a resource metric. The system and method further include refreshing the plurality of sub-arrays based upon the refresh interval determined for the plurality of bit positions, and dynamically updating the refresh interval for the plurality of bit positions upon receiving a new fidelity metric or a new resource metric.

Abstract: A system and method include determining, by a memory controller associated with a memory device, a value of a parameter of a write pulse for a plurality of bits of a B-bit word to be stored in the memory device. The value of the parameter is based upon a relative importance of a bit position of the plurality of bits in the B-bit word to a performance of a machine learning or signal processing task involving the B-bit word, a fidelity metric, and a resource metric. The system and method also include writing each of the plurality of bits of the B-bit word in a different sub-array of the memory device using the write pulse generated based on the value of the parameter determined for a particular one of the plurality of bits.

Abstract: A system and method for training base classifiers in a boosting algorithm includes optimally training base classifiers considering an unreliability model, and then using a scheme with an aggregator decoder that reverse-flips inputs using inter-classifier redundancy introduced in training.

Abstract: A system and method for allocating computational resources includes a plurality of classifiers, a memory array, and a memory controller to allocate memory from the memory array to each of the plurality of classifier. The system and method also include an optimization processor to determine an optimized bit precision value for at least one of the plurality of classifiers based upon a relative importance of the plurality of classifiers. The memory controller allocates the memory from the memory array to the plurality of classifiers based upon the determined optimized bit precision value.

Abstract: A system and method for refreshing memory cells of a memory device includes storing each bit of a B-bit word in a different sub-array of a memory device. Each of the bits is associated with a bit position, and the memory device includes a plurality of sub-arrays. The system and method also include determining a refresh interval for a plurality of the bit positions based upon a relative importance of the plurality of the bit positions to a performance of a machine learning or signal processing task involving the B-bit word. The refresh interval is based upon a fidelity metric and a resource metric. The system and method further include refreshing the plurality of sub-arrays based upon the refresh interval determined for the plurality of bit positions, and dynamically updating the refresh interval for the plurality of bit positions upon receiving a new fidelity metric or a new resource metric.

Abstract: Methods are described that allow disk drives, such as shingle-written magnetic recording (SMR) drives, to recover an Indirection Address Table mapping of LBAs to PBAs after an emergency power off (EPO). Indirection Address Table (IAT) snapshots are periodically written inline with user data stores, and in one embodiment Cumulative Delta Lists (CDLs) with incremental address update information are stored between snapshots. In an embodiment of the invention, when an imminent loss of power is detected, the current CDL, covering IAT updates not yet written to disk, is saved to a nonvolatile memory. The IAT snapshots combined with the set of CDLs provide the information needed to recreate the current Indirection Address Table when power is restored after an emergency power loss. In an alternative embodiment the CDL is obviated by including metadata in the sector that encodes the address indirection mapping and the last snapshot ID.

Abstract: A multi-level cell flash memory storage device has cells wherein different charge levels represent different information. The storage device can read stored charge from one or more cells, store a rewrite generation value for a group of a plurality of cells in a block of cells, and write to cells, wherein writing to one or more cells without an erase includes an increment of the rewrite generation value, and includes circuitry for reading from cells, including circuitry for reading the rewrite generation value. The storage device can include circuitry for reading from cells includes within the multi-level cell flash memory storage device logic for calculating a stored value of the cells using the rewrite generation value and relative levels of charge on a plurality of cells. The storage device can track hot addresses and cold addresses and perform static or dynamic wear leveling based on accumulated rewrite generation values.

Abstract: A method is described for allowing disk drives, such as shingle-written magnetic recording (SMR) drives, to be shipped for customer use with portions of the magnetic media being left untested. The testing is then completed by the drive self-testing in the field. The drive is made functional at the factory by fully testing at least one operational set of regions including an I-region, an E-region and a write cache region. The operational set of regions works as a separate self-contained virtual disk drive and can be used immediately. The remaining untested areas on the media can be tested in the field by a background task and/or when the first write command is received that requires a new track or operational set of regions (on-the fly testing).

Abstract: A method is described for allowing disk drives, such as shingle-written magnetic recording (SMR) drives, to be shipped for customer use with portions of the magnetic media being left untested. The testing is then completed by the drive self-testing in the field. The drive is made functional at the factory by fully testing at least one operational set of regions including an I-region, an E-region and a write cache region. The operational set of regions works as a separate self-contained virtual disk drive and can be used immediately. The remaining untested areas on the media can be tested in the field by a background task and/or when the first write command is received that requires a new track or operational set of regions (on-the fly testing).

Abstract: An embodiment of the present invention implements some or all major servo subfunctions for a storage device in integrated servo fields comprising sequences of encoded bits having selected mathematical properties. The integrated servo field is composed of a number of encoded sequences, which are members of a selected sequence set that is constrained to preferably provide some or all of the following functions: the Servo Track Mark (STM), the Position Error Signal (PES) and positional information such as the track-ID. In one embodiment the plurality sequences encoding a location identifier such as a track-ID are distributed across a set of servo wedges. A method of encoding the location identifier using a Chinese Remainder Theorem is described.

Abstract: Methods are described that allow disk drives, such as shingle-written magnetic recording (SMR) drives, to recover an Indirection Address Table mapping of LBAs to PBAs after an emergency power off (EPO). Indirection Address Table (IAT) snapshots are periodically written inline with user data stores, and in one embodiment Cumulative Delta Lists (CDLs) with incremental address update information are stored between snapshots. In an embodiment of the invention, when an imminent loss of power is detected, the current CDL, covering IAT updates not yet written to disk, is saved to a nonvolatile memory. The IAT snapshots combined with the set of CDLs provide the information needed to recreate the current Indirection Address Table when power is restored after an emergency power loss. In an alternative embodiment the CDL is obviated by including metadata in the sector that encodes the address indirection mapping and the last snapshot ID.

Abstract: Error correction is tailored for the use of an ECC for correcting asymmetric errors with low magnitude in a data device, with minimal modifications to the conventional data device architecture. The technique permits error correction and data recovery to be performed with reduced-size error correcting code alphabets. For particular cases, the technique can reduce the problem of constructing codes for correcting limited magnitude asymmetric errors to the problem of constructing codes for symmetric errors over small alphabets. Also described are speed up techniques for reaching target data levels more quickly, using more aggressive memory programming operations.