Abstract: There is provided an apparatus in which processing circuitry performs processing in one of a fixed number of at least two domains, one of the domains being subdivided into a variable number of execution environments. Memory translation circuitry, in response to a memory access request to a given memory address, determines a given encryption environment identifier associated with the one of the execution environments and forwards the memory access request together with the given encryption environment identifier. Storage circuitry stores a plurality of entries, each associated with an associated encryption environment identifier and an associated memory address. The storage circuitry includes determination circuitry that determines, in at least one enabled mode of operation, whether the given encryption environment identifier differs from the associated encryption environment identifier associated with one of the entries associated with the given memory address.

Abstract: An apparatus comprises request receiving circuitry to receive a given memory system request specifying a target address in a given physical address space and a target memory encryption context identifier (MECID) indicative of a selected memory encryption context associated with the memory system request. Snoop filtering circuitry determines whether a snoop request is to be transmitted to a given caching agent in response to the given memory system request. The snoop filtering circuitry determines, based on the target MECID of the given memory system request and on snoop filtering information associated with the given caching agent, whether the target MECID is a snoop-not-required MECID for the given caching agent. In response to determining that the target MECID is a snoop-not-required MECID for the given caching agent, the snoop filtering circuitry suppresses transmission of a snoop request to the given caching agent in response to the given memory system request.

Abstract: Apparatus, method and code for fabrication of an apparatus. The apparatus comprises address translation circuitry (116) to translate virtual addresses to physical addresses in response to advance address translation requests issued by devices (105) on behalf of software contexts (125). The apparatus also comprises translated access control circuitry (117) to control access to memory (110) in response to translated access requests issued by the devices (105) on behalf of the software contexts (125), based on permissions information defined in a device permission table (220), wherein the corresponding access permissions provide information for checking whether translated access requests from a plurality of software contexts are prohibited.

Abstract: Address translation circuitry 16 translates a virtual address specified by a memory access request issued by requester circuitry into a target physical address (PA). Requester-side filtering circuitry 20 performs a granule protection lookup based on the target PA and a selected physical address space (PAS) associated with the memory access request, to determine whether to allow the memory access request to be passed to a cache or interconnect. In the granule protection lookup, the requester-side filtering circuitry obtains granule protection information corresponding to a target granule of physical addresses including the target PA, which indicates at least one allowed PAS associated with the target granule, and blocks the memory access request when the granule protection information indicates that the selected PAS is not an allowed PAS.

Abstract: Address translation circuitry (16) translates a virtual address specified by a memory access request issued by requester circuitry into a target physical address (PA). Requester-side filtering circuitry (20) performs a granule protection lookup based on the target PA and a selected physical address space (PAS) associated with the memory access request, to determine whether to allow the memory access request to be passed to a cache or interconnect. In the granule protection lookup, the requester-side filtering circuitry obtains granule protection information corresponding to a target granule of physical addresses including the target PA, which indicates at least one allowed PAS associated with the target granule, and blocks the memory access request when the granule protection information indicates that the selected PAS is not an allowed PAS.

Abstract: The disclosure relates to techniques for controlling Specific Absorption Rate (SAR) of radio energy transmission. In particular, the disclosure relates to a radio device and a method for controlling radio energy transmission of a plurality of radio entities to comply with a predefined SAR requirement. Such a radio device includes: a plurality of radio entities configured to transmit radio energy; and a controller configured to control the radio energy transmission of the plurality of radio entities to comply with a predefined Specific Absorption Rate, SAR, requirement, wherein the controller is configured to enable at least two radio entities of the plurality of radio entities operating concurrently based on a shared SAR transmission power restriction which allows the at least two radio entities transmitting concurrently at a predefined duty cycle, in particular at 100% duty cycle, without violating the SAR requirement.

Abstract: Methods and apparatus to mitigate coexistence interference in a wireless network are disclosed. An example apparatus includes a station component interface to receive an expected transmission power from an access point; an index processor to determine a set of preferred resource unit (RU) indexes from a set of available RU indexes for at least one of (A) uplink transmission to the access point based on a comparison of allowable transmission power and the expected transmission power or (B) downlink reception based on a comparison of a noise floor to a noise threshold; and the station component interface to transmit a message including the preferred RU indexes to the access point.

Abstract: Processing circuitry 10 performs processing in one of at least three domains 82, 84, 86, 88. Address translation circuitry 16 translates a virtual address of a memory access performed from a current domain to a physical address in one of a plurality of physical address spaces 61 selected based at least on the current domain. The domains include a root domain 82 for managing switching between other domains. The physical address spaces 61 include a root physical address space associated with the root domain 82, separate from physical address spaces associated with other domains.

Abstract: Processing circuitry (10) performs processing in one of at least three domains (82, 84, 86, 88). Address translation circuitry (16) translates a virtual address of a memory access performed from a current domain to a physical address in one of a plurality of physical address spaces (61) selected based at least on the current domain. The domains include a root domain (82) for managing switching between other domains. The physical address spaces (61) include a root physical address space associated with the root domain (82), separate from physical address spaces associated with other domains.

Abstract: An apparatus and method are provided, the apparatus comprising: interconnect circuitry to couple a device to one or more processing elements, each processing element operating in a trusted execution environment; and secure stashing decision circuitry to receive stashing transactions from the device and to redirect permitted stashing transactions to a given storage structure accessible to at least one of the one or more processing elements. The secure stashing decision circuitry is configured, in response to receiving a given stashing transaction, to determine whether the given stashing transaction comprises a trusted execution environment identifier associated with a given trusted execution environment, and to treat the given stashing transaction as a permitted stashing transaction when redirection requirements, dependent on the trusted execution environment identifier, are met.

Abstract: An apparatus comprising translation circuitry to perform a translation operation to generate a translated second memory address within a second memory address space as a translation of a first memory address within a first memory address space, in which the translation circuitry is configured to generate the translated second memory address in dependence upon translation information stored at one or more translation information addresses; permission circuitry to perform an operation to detect permission information to indicate, for a given second memory address, whether memory access is permitted to the given second memory address; and access circuitry to allow access to data stored at the given second memory address when the permission information indicates that memory access is permitted to the given second memory address.

Abstract: An apparatus has memory management circuitry to control access to a memory system based on access control information defined in table entries of a table structure comprising at least two levels of access control table. Table accessing circuitry accesses the table structure to obtain the access control information corresponding to a target address. For a given access control table at a given level of the table structure other than a starting level, the table accessing circuitry selects a selected table entry of the given access control table corresponding to the target address, based on an offset portion of the target address. A size of the offset portion is selected based on a variable nesting control parameter specified in a table entry of a higher-level access control table at a higher level of the table structure than the given access control table.

Abstract: The disclosure relates to techniques for controlling Specific Absorption Rate (SAR) of radio energy transmission. In particular, the disclosure relates to a radio device and a method for controlling radio energy transmission of a plurality of radio entities to comply with a predefined SAR requirement. Such a radio device includes: a plurality of radio entities configured to transmit radio energy; and a controller configured to control the radio energy transmission of the plurality of radio entities to comply with a predefined Specific Absorption Rate, SAR, requirement, wherein the controller is configured to enable at least two radio entities of the plurality of radio entities operating concurrently based on a shared SAR transmission power restriction which allows the at least two radio entities transmitting concurrently at a predefined duty cycle, in particular at 100% duty cycle, without violating the SAR requirement.

Abstract: An apparatus has address translation circuitry to translate a target virtual address (VA) specified by a memory access request into a target physical address, first/second translation table address storage circuitry to store first/second translation table addresses; and protected region defining data storage circuitry to store region defining data specifying at least one protected region of virtual address space. In response to the memory access request: when the target VA is in the protected region(s), the address translation circuitry translates the target VA based on address translation data from a first translation table structure identified by the first translation table address. When the target VA is outside the protected region(s), the target VA is translated based on address translation data from a second translation table structure identified by the second translation table address.

Abstract: An apparatus (4) comprises memory access circuitry (12) to control access to data stored in a memory; and memory integrity checking circuitry (20) to verify integrity of data stored in the memory, using an integrity tree (26) in which the association between parent and child nodes is provided by a pointer. This helps to reduce the memory footprint of the tree.

Abstract: Apparatus comprising translation circuitry to perform a translation operation to generate a translated second memory address within a second memory address space as a translation of a first memory address within a first memory address space, in which the translation circuitry is configured to generate the translated second memory address in dependence upon translation information stored at one or more translation information addresses; permission circuitry to perform an operation to detect permission information to indicate, for a given second memory address, whether memory access is permitted to the given second memory address; and access circuitry to allow access to data stored at the given second memory address when the permission information indicates that memory access is permitted to the given second memory address.

Abstract: An apparatus has memory management circuitry to control access to a memory system based on access control information defined in table entries of a table structure comprising at least two levels of access control table. Table accessing circuitry accesses the table structure to obtain the access control information corresponding to a target address. For a given access control table at a given level of the table structure other than a starting level, the table accessing circuitry selects a selected table entry of the given access control table corresponding to the target address, based on an offset portion of the target address. A size of the offset portion is selected based on a variable nesting control parameter specified in a table entry of a higher-level access control table at a higher level of the table structure than the given access control table.

Abstract: The disclosure relates to techniques for controlling Specific Absorption Rate (SAR) of radio energy transmission. In particular, the disclosure relates to a radio device and a method for controlling radio energy transmission of a plurality of radio entities to comply with a predefined SAR requirement. Such a radio device includes: a plurality of radio entities configured to transmit radio energy; and a controller configured to control the radio energy transmission of the plurality of radio entities to comply with a predefined Specific Absorption Rate, SAR, requirement, wherein the controller is configured to enable at least two radio entities of the plurality of radio entities operating concurrently based on a shared SAR transmission power restriction which allows the at least two radio entities transmitting concurrently at a predefined duty cycle, in particular at 100% duty cycle, without violating the SAR requirement.

Abstract: Address translation circuitry (16) translates a virtual address specified by a memory access request issued by requester circuitry into a target physical address (PA). Requester-side filtering circuitry (20) performs a granule protection lookup based on the target PA and a selected physical address space (PAS) associated with the memory access request, to determine whether to allow the memory access request to be passed to a cache or interconnect. In the granule protection lookup, the requester-side filtering circuitry obtains granule protection information corresponding to a target granule of physical addresses including the target PA, which indicates at least one allowed PAS associated with the target granule, and blocks the memory access request when the granule protection information indicates that the selected PAS is not an allowed PAS.

Abstract: There is provided a data processing apparatus, which is suitable for verifying memory systems. Processing circuitry issues a plurality of memory access requests to a plurality of addresses in a memory. Point-of-trust circuitry receives the memory access requests from the processing circuitry via a first set of intermediate circuits. Secure channel circuitry enables secure communication of a correspondence between the plurality of addresses from the processing circuitry to the point-of-trust circuitry. The point-of-trust circuitry determines whether the addresses in the memory of the memory access requests received via the first set of intermediate circuits have a predetermined relationship based on the correspondence.