Abstract: A cartridge of an e-vaping device includes a housing extending in a longitudinal direction, a reservoir in the housing, a heater in the housing, and an absorbent material at least partially surrounding the sinusoidal shaped member. The reservoir is configured to store a pre-vapor formulation. The heater has a sinusoidal shaped member translating about an elliptical shape to define a channel there through. The absorbent material is in fluid communication with the reservoir.

Abstract: A cartridge of an e-vaping device includes a housing extending in a longitudinal direction, a reservoir in the housing, a heater in the housing, and an absorbent material at least partially surrounding the sinusoidal shaped member. The reservoir is configured to store a pre-vapor formulation. The heater has a sinusoidal shaped member translating about an elliptical shape to define a channel there through. The absorbent material is in fluid communication with the reservoir.

Abstract: Methods and systems for latency optimized ATS usage are disclosed. Aspects of one method may include communicating a memory access request using an untranslated address and also an address translation request using the same untranslated address, where the translation request may be sent without waiting for a result of the memory access request. The memory access request and the address translation request may be made in either order. A translation agent may be used to translate the untranslated address, and the translated address may be communicated to the device that made the memory access request. The translated address may also be used to make the memory access. Accordingly, by communicating the translated address without having to wait for completion of the memory access, or vice versa, the requesting device may reduce latency for memory accesses when using untranslated addresses.

Abstract: Methods and systems for latency optimized ATS usage are disclosed. Aspects of one method may include communicating a memory access request using an untranslated address and also an address translation request using the same untranslated address, where the translation request may be sent without waiting for a result of the memory access request. The memory access request and the address translation request may be made in either order. A translation agent may be used to translate the untranslated address, and the translated address may be communicated to the device that made the memory access request. The translated address may also be used to make the memory access. Accordingly, by communicating the translated address without having to wait for completion of the memory access, or vice versa, the requesting device may reduce latency for memory accesses when using untranslated addresses.

Abstract: An embedded memory unit includes a memory array having a design size given by an integer n, the array including a matrix of memory cells arranged in n+1 lines, and selection circuitry, coupled to select n of the n+1 lines to which data are to be written and from which the data are to be read. A built-in self-test (BIST) circuit is coupled to test the memory array and to generate a binary pass/fail output. A repair machine is coupled to receive the binary output of the BIST circuit and to drive the selection circuitry to select different sets of n of the lines while driving the BIST circuit to test the memory array, so as to find one of the different sets for which the binary output indicates that the array has passed the self-test.

Abstract: An embedded memory unit includes a memory array having a design size given by an integer n, the array including a matrix of memory cells arranged in n+1 lines, and selection circuitry, coupled to select n of the n+1 lines to which data are to be written and from which the data are to be read. A built-in self-test (BIST) circuit is coupled to test the memory array and to generate a binary pass/fail output. A repair machine is coupled to receive the binary output of the BIST circuit and to drive the selection circuitry to select different sets of n of the lines while driving the BIST circuit to test the memory array, so as to find one of the different sets for which the binary output indicates that the array has passed the self-test.