Patents by Inventor Yuval Kirschner
Yuval Kirschner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11495313Abstract: An integrated circuit (IC) includes a non-volatile memory and boot circuitry. The boot circuitry is configured to boot the IC, including reading from the non-volatile memory one or more values indicative of whether production testing of the IC was completed successfully, and initiating a responsive action if the one or more values indicate that the production testing was not completed successfully.Type: GrantFiled: September 1, 2021Date of Patent: November 8, 2022Assignee: NUVOTON TECHNOLOGY CORPORATIONInventor: Yuval Kirschner
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Patent number: 11436315Abstract: A computer system includes a memory, a processor and authentication enforcement hardware. The processor is configured to execute software, including an authentication program that authenticates data stored in the memory. The authentication enforcement hardware is coupled to the processor and is configured to verify that (i) the processor executes the authentication program periodically with at least a specified frequency, and that (ii) the authentication program successfully authenticates the data.Type: GrantFiled: August 15, 2019Date of Patent: September 6, 2022Assignee: NUVOTON TECHNOLOGY CORPORATIONInventor: Yuval Kirschner
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Patent number: 11366899Abstract: A secure Integrated Circuit (IC) includes functional circuitry, and protection circuitry configured to protect the functional circuitry against fault-injection attacks. The protection circuitry includes a plurality of digital detection cells, and protection logic. The detection cells have respective inputs and outputs and are connected output-to-input in at least a chain. In response to a fault-injection attack, a given detection cell in the chain is configured to toggle an output that drives an input of a subsequent detection cell in the chain, thereby causing a pulse to propagate along the chain. The protection logic is configured to receive the pulse from the chain and initiate a responsive action.Type: GrantFiled: February 18, 2020Date of Patent: June 21, 2022Assignee: NUVOTON TECHNOLOGY CORPORATIONInventors: Yuval Kirschner, Ziv Hershman, Tamir Golan
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Patent number: 11188306Abstract: A Random-Number Generator (RNG) includes a first plurality of High-Frequency (HF) clock generators, a second plurality of Low-Frequency (LF) clock generators, a third plurality of Digital Random-Number Generator circuits (DRNGs), and a multiplexer. The HF clock generators are configured to generate respective HF clock signals in a first frequency range. The LF clock generators are configured to generate respective LF clock signals in a second frequency range, lower than the first frequency range. Each DRNG is configured to derive a respective random-bit sequence from (i) a respective HF clock signal taken from among the HF clock signals and (ii) a respective LF clock signal taken from among the HF clock signals. The multiplexer is configured to produce an output sequence of random bits from random-bit sequences generated by the DRNGs.Type: GrantFiled: August 18, 2020Date of Patent: November 30, 2021Assignee: NUVOTON TECHNOLOGY CORPORATIONInventors: Yuval Kirschner, Tamir Golan
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Publication number: 20210256119Abstract: A secure Integrated Circuit (IC) includes functional circuitry, and protection circuitry configured to protect the functional circuitry against fault-injection attacks. The protection circuitry includes a plurality of digital detection cells, and protection logic. The detection cells have respective inputs and outputs and are connected output-to-input in at least a chain. In response to a fault-injection attack, a given detection cell in the chain is configured to toggle an output that drives an input of a subsequent detection cell in the chain, thereby causing a pulse to propagate along the chain. The protection logic is configured to receive the pulse from the chain and initiate a responsive action.Type: ApplicationFiled: February 18, 2020Publication date: August 19, 2021Inventors: Yuval Kirschner, Ziv Hershman, Tamir Golan
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Publication number: 20210049258Abstract: A computer system includes a memory, a processor and authentication enforcement hardware. The processor is configured to execute software, including an authentication program that authenticates data stored in the memory. The authentication enforcement hardware is coupled to the processor and is configured to verify that (i) the processor executes the authentication program periodically with at least a specified frequency, and that (ii) the authentication program successfully authenticates the data.Type: ApplicationFiled: August 15, 2019Publication date: February 18, 2021Inventor: Yuval Kirschner
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Publication number: 20200341058Abstract: Embodiments of the present invention include an apparatus including a debug interface, a counter, and debug-enabling circuitry. The debug-enabling circuitry is configured to receive a debug-enabling input, and responsively to the debug-enabling input, enable the debug interface and start the counter. The counter is configured to output an output signal that causes the debug interface to become disabled, following a predetermined duration from a time at which the counter was started. Other embodiments are also described.Type: ApplicationFiled: April 28, 2019Publication date: October 29, 2020Inventor: Yuval Kirschner
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Patent number: 10778235Abstract: Described embodiments include a system, including clocked circuitry, an oscillator controller, and an oscillator, configured to output an output clock signal that clocks the clocked circuitry and is fed to the oscillator controller. The oscillator controller is configured to control the oscillator responsively to an output frequency of the output clock signal. The system further includes power-management circuitry, configured to cause the clocked circuitry to sleep by disabling the oscillator, and waking circuitry, configured to intermittently enable the oscillator such that the oscillator controller intermittently, while the clocked circuitry sleeps, causes the output frequency to converge to a target frequency by controlling the oscillator. Other embodiments are also described.Type: GrantFiled: October 28, 2018Date of Patent: September 15, 2020Assignee: NUVOTON TECHNOLOGY CORPORATIONInventor: Yuval Kirschner
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Publication number: 20200136629Abstract: Described embodiments include a system, including clocked circuitry, an oscillator controller, and an oscillator, configured to output an output clock signal that clocks the clocked circuitry and is fed to the oscillator controller. The oscillator controller is configured to control the oscillator responsively to an output frequency of the output clock signal. The system further includes power-management circuitry, configured to cause the clocked circuitry to sleep by disabling the oscillator, and waking circuitry, configured to intermittently enable the oscillator such that the oscillator controller intermittently, while the clocked circuitry sleeps, causes the output frequency to converge to a target frequency by controlling the oscillator. Other embodiments are also described.Type: ApplicationFiled: October 28, 2018Publication date: April 30, 2020Inventor: Yuval Kirschner
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Patent number: 10249579Abstract: An electronic apparatus includes, a substrate, one or more routing layers, and an active shield layer. The substrate includes active devices. The routing layers are electrically connected to the active devices and are configured to route electrical signals to and from the active devices. The active shield layer is disposed within a routing layer nearest to the substrate, the active shield layer includes metallic traces configured conduct active-shield signals that provide an indication of an attack on the apparatus.Type: GrantFiled: April 25, 2017Date of Patent: April 2, 2019Assignee: NUVOTON TECHNOLOGY CORPORATIONInventors: Yuval Kirschner, Arnon Sharlin
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Publication number: 20180308808Abstract: An electronic apparatus includes, a substrate, one or more routing layers, and an active shield layer. The substrate includes active devices. The routing layers are electrically connected to the active devices and are configured to route electrical signals to and from the active devices. The active shield layer is disposed within a routing layer nearest to the substrate, the active shield layer includes metallic traces configured conduct active-shield signals that provide an indication of an attack on the apparatus.Type: ApplicationFiled: April 25, 2017Publication date: October 25, 2018Inventors: Yuval Kirschner, Arnon Sharlin
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Publication number: 20180039427Abstract: An apparatus for data storage includes an interface for communicating with a memory, and encoding circuitry. The memory incurs a first bit-programming duration in programming a first bit value, and incurs a second bit-programming duration, longer than the first bit-programming duration, in programming a second bit value opposite from the first bit value. The encoding circuitry is configured to receive input data words for storage in the memory, to encode the input data words so as to produce respective encoded data words, wherein the encoded data words are (i) larger than the input data words by multiple bits, but (ii) are programmed in the memory with a shorter programming duration than the input data words, and to send the encoded data words via the interface for storage in the memory.Type: ApplicationFiled: August 8, 2016Publication date: February 8, 2018Inventor: Yuval Kirschner
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Patent number: 9825587Abstract: An electronic circuit includes a first oscillator, a second oscillator and ancillary circuitry. The first oscillator is configured to generate a first clock signal and has a first wake-up delay. The second oscillator is configured to generate a second clock signal and has a second wake-up delay that is shorter than the first wake-up delay. The ancillary circuitry is configured to provide the second clock signal as an output clock signal during wake-up of the first oscillator, and, following the first wake-up delay, to provide the first clock signal as the output clock signal.Type: GrantFiled: July 21, 2016Date of Patent: November 21, 2017Assignee: NUVOTON TECHNOLOGY CORPORATIONInventors: Yuval Kirschner, Nimrod Peled, Michal Schramm, Victor Adrian Flachs, Ofer Cohen
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Patent number: 8543755Abstract: An embedded controller includes a microcontroller core, a first bus interface that does not support bus arbitration, a second bus interface and memory control circuitry. The first bus interface is configured to receive and transmit memory transactions from and to a Central Processing Unit (CPU) chipset. The second bus interface is configured to communicate with a memory and to transfer the memory transactions of the CPU chipset to and from the memory. The memory control circuitry is configured to evaluate a starvation condition that identifies an inability of the microcontroller core to access the memory via the second bus interface due to the memory transactions transferred between the CPU chipset and the memory via the first and second bus interfaces, and to invoke a predefined corrective action when the starvation condition is met.Type: GrantFiled: January 29, 2012Date of Patent: September 24, 2013Assignee: Nuvoton Technology CorporationInventors: Moshe Alon, Ilia Stolov, Erez Naory, Nir Tasher, Yuval Kirschner, Michal Schramm
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Publication number: 20120239848Abstract: An embedded controller includes a microcontroller core, a first bus interface that does not support bus arbitration, a second bus interface and memory control circuitry. The first bus interface is configured to receive and transmit memory transactions from and to a Central Processing Unit (CPU) chipset. The second bus interface is configured to communicate with a memory and to transfer the memory transactions of the CPU chipset to and from the memory. The memory control circuitry is configured to evaluate a starvation condition that identifies an inability of the microcontroller core to access the memory via the second bus interface due to the memory transactions transferred between the CPU chipset and the memory via the first and second bus interfaces, and to invoke a predefined corrective action when the starvation condition is met.Type: ApplicationFiled: January 29, 2012Publication date: September 20, 2012Applicant: NUVOTON TECHNOLOGY CORPORATIONInventors: Moshe Alon, Ilia Stolov, Erez Naory, Nir Tasher, Yuval Kirschner, Michal Schramm
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Patent number: 7865646Abstract: An improved system is described for allowing an embedded controller and a host processor to share access to modules in a computer system. The shared access system of the present invention enables exclusive, one-at-a-time access by a processor to a module and concurrent access by more than one processor to a module. An internal bus with two power sources is used to allow continued access by one of the processors when one of the two power sources is not providing power. Asynchronous clocking is provided to allow increased throughput to modules. An example of a protocol that allows an embedded controller to access more than one module is also described.Type: GrantFiled: July 20, 2006Date of Patent: January 4, 2011Assignee: National Semiconductor CorporationInventors: Ohad Falik, Yehezkel Friedman, Victor Flachs, Yuval Kirschner
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Patent number: 7089339Abstract: An improved system is described for allowing an embedded controller and a host processor to share access to modules in a computer system. The shared access system of the present invention enables exclusive, one-at-a-time access by a processor to a module and concurrent access by more than one processor to a module. An internal bus with two power sources is used to allow continued access by one of the processors when one of the two power sources is not providing power. Asynchronous clocking is provided to allow increased throughput to modules. An example of a protocol that allows an embedded controller to access more than one module is also described.Type: GrantFiled: March 16, 2001Date of Patent: August 8, 2006Assignee: National Semiconductor CorporationInventors: Ohad Falik, Yehezkel Friedman, Victor Flachs, Yuval Kirschner
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Publication number: 20020133655Abstract: An improved system is described for allowing an embedded controller and a host processor to share access to modules in a computer system. The shared access system of the present invention enables exclusive, one-at-a-time access by a processor to a module and concurrent access by more than one processor to a module. An internal bus with two power sources is used to allow continued access by one of the processors when one of the two power sources is not providing power. Asynchronous clocking is provided to allow increased throughput to modules. An example of a protocol that allows an embedded controller to access more than one module is also described.Type: ApplicationFiled: March 16, 2001Publication date: September 19, 2002Inventors: Ohad Falik, Yehezkel Friedman, Victor Flachs, Yuval Kirschner