Patents by Inventor Yuval Peled

Yuval Peled has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11343358
    Abstract: At least a packet header of a packet received by a network device is provided to a programmable header alteration engine that includes a hardware input processor implemented in hardware and a programmable header alteration processor configured to execute computer readable instructions stored in a program memory. The hardware input processor determines whether the packet header is to be provided to a processing path coupled to the programmable header alteration processor or to be diverted to a bypass path that bypasses the programmable header alteration processor, and the packet header is provided to the processing path or to the bypass path based on the determination. The packet header is selectively i) processed by the programmable header alteration processor when the packet header is provided to the processing path and ii) not processed by the programmable header alteration processor when the packet header is provided to the bypass path.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: May 24, 2022
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventors: Yuval Peled, Doron Schupper, Ilan Yerushalmi, Rami Zemach
  • Patent number: 10581433
    Abstract: An integrated circuit device includes dispatcher circuitry that receives signals from a first number of sources, multiplexes the signals into a single mixed signal in a predetermined order, and transmits the mixed signal to a destination via a mixed signal interface having an arbitrary length and operating at an interface clock frequency equal to a product of a device clock frequency and the first number. A second number of samplers is disposed in series along the mixed signal interface, outputting a sampled mixed signal synchronized to the interface clock. A chain of tracking elements in series, corresponding in number to the second number, outputs a tracking indication separate from the sampled mixed signal. Capture circuitry demultiplexes the sampled mixed signal into a plurality of demultiplexed signals, according to a starting point based on the tracking indication, onto a plurality of signal buses corresponding in number to the first number.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: March 3, 2020
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventors: Lior Moheban, Jacob Jul Schroder, Yuval Peled
  • Patent number: 9894861
    Abstract: A determinate castor is provided. Also provided are methods of generating and using same as well as products thereof.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: February 20, 2018
    Assignee: Kaiima Bio Agritech Ltd.
    Inventors: Yuval Peles, Alon Lerner, Asaf Meiri, Itay Dodek, Sahar Gelfman, Aviad Freiman, Yaniv Lerenthal, Lilah Rothem
  • Patent number: 9672042
    Abstract: A processing system comprises a processing device; a first instruction set encoded in a first encoding space and comprising one or more first instructions; a second instruction set encoded in a second encoding space different from the first encoding space and comprising two or more orthogonal second instructions; and an instruction encoder arranged to encode and encapsulate subsets of the second instructions in instruction containers, each instruction container sized to comprise a plurality of the second instructions.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: June 6, 2017
    Assignee: NXP USA, INC.
    Inventors: Roy Glasner, Itzhak Barak, Yuval Peled, Idan Rozenberg, Lev Vaskevich
  • Patent number: 9606802
    Abstract: A processor system is adapted to carry out a predicate swap instruction of an instruction set to swap, via a data pathway, predicate data in a first predicate data location of a predicate register with data in a corresponding additional predicate data location of a first additional predicate data container and to swap, via a data pathway, predicate data in a second predicate storage location of the predicate register with data in a corresponding additional predicate data location in a second additional predicate data container.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: March 28, 2017
    Assignee: NXP USA, INC.
    Inventors: Yuval Peled, Itzhak Barak, Uri Dayan, Amir Kleen, Idan Rozenberg
  • Patent number: 9471321
    Abstract: There is provided a method for controlling fetch-ahead of Fetch Sets into a decoupling First In First Out (FIFO) buffer of a Variable Length Execution Set (VLES) processor architecture, wherein a Fetch Set comprises at least a portion of a VLES group available for dispatch to processing resources within the VLES processor architecture, comprising, for each cycle, determining a number of VLES groups available for dispatch from previously pre-fetched Fetch Sets, and only requesting a fetch-ahead of a next Fetch Set in the next cycle if one of a select set of criteria related to the number of VLES groups available for dispatch is true.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: October 18, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Lev Vaskevich, Mark Elnekave, Yuval Peled, Idan Rozenberg
  • Patent number: 8644623
    Abstract: Various embodiments provide approaches for measuring the rendering times of a webpage that can be browser-independent. In at least some embodiments, as a web page is rendered, video data of the webpage is captured and analyzed to ascertain when the webpage, or portions thereof, have likely been completely rendered. In at least some embodiments, image processing can be performed on captured video data to ascertain, from observed pixel changes over time, when the webpage has likely been rendered.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: February 4, 2014
    Assignee: Microsoft Corporation
    Inventors: Meir Shmouely, Omer Rosenbaum, Gregory Bershansky, Yuval Peled, M. David Fields, Cenk Ergan, Michael D. Decker, Aaron Rodriguez Hernandez, Matthew P. Kotsenas, Jason J. Weber, Yi Ming Zhou, Kieran Chin Cheong, Kelly Laurence Ford
  • Publication number: 20140025931
    Abstract: There is provided a method for controlling fetch-ahead of Fetch Sets into a decoupling First In First Out (FIFO) buffer of a Variable Length Execution Set (VLES) processor architecture, wherein a Fetch Set comprises at least a portion of a VLES group available for dispatch to processing resources within the VLES processor architecture, comprising, for each cycle, determining a number of VLES groups available for dispatch from previously pre-fetched Fetch Sets, and only requesting a fetch-ahead of a next Fetch Set in the next cycle if one of a select set of criteria related to the number of VLES groups available for dispatch is true.
    Type: Application
    Filed: March 30, 2011
    Publication date: January 23, 2014
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Lev Vaskevich, Mark Elnekave, Yuval Peled, Idan Rozenberg
  • Publication number: 20140013087
    Abstract: A processor system is adapted to carry out a predicate swap instruction of an instruction set to swap, via a data pathway, predicate data in a first predicate data location of a predicate register with data in a corresponding additional predicate data location of a first additional predicate data container and to swap, via a data pathway, predicate data in a second predicate storage location of the predicate register with data in a corresponding additional predicate data location in a second additional predicate data container.
    Type: Application
    Filed: March 25, 2011
    Publication date: January 9, 2014
    Applicant: Freescale Semiconductor, Inc
    Inventors: Yuval Peled, Itzhak Barak, Uri Dayan, Amir Kleen, Idan Rozenberg
  • Publication number: 20130326200
    Abstract: An integrated circuit device comprising at least one instruction processing module arranged to compare validation data with data stored within a target register upon receipt of a load validation instruction. Wherein, the instruction processing module is further arranged to proceed with execution of a next sequential instruction if the validation data matches the stored data within the target register, and to load the validation data into the target register if the validation data does not match the stored data within the target register.
    Type: Application
    Filed: February 11, 2011
    Publication date: December 5, 2013
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Amir Kleen, Itzhak Barak, Yuval Peled, Idan Rozenberg, Doron Schupper
  • Publication number: 20130290686
    Abstract: An integrated circuit device comprises at least one instruction processing module arranged to perform branch predication. The at least one instruction processing module comprises at least one predicate calculation module arranged to receive as an input at least one result vector for a predicate function and at least one conditional parameter value therefor and output a predicate result value from the at least one result vector based at least partly on the at least one received conditional parameter value.
    Type: Application
    Filed: January 21, 2011
    Publication date: October 31, 2013
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Yuval Peled, Itzhak Barak, Idan Rozenberg, Doron Schupper, Lev Vaskevich
  • Patent number: 8533441
    Abstract: A method for managing branch instructions, the method includes: providing, to pipeline stages of a processor, multiple variable length groups of instructions; wherein each pipeline stage executes a group of instruction during a single execution cycle; receiving, at a certain execution cycle, multiple instruction fetch requests from multiple pipeline stages, each pipeline stage that generates an instruction fetch request stores a variable length group of instructions that comprises a branch instruction; sending to the fetch unit an instruction fetch command that is responsive to a first in order branch instruction in the pipeline stages; wherein if the first in order fetch command is a conditional fetch command then the instruction fetch command comprises a resolved target address; wherein the sending of the instruction fetch command is restricted to a single instruction fetch command per a single execution cycle.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: September 10, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yuval Peled, Itzhak Barak, Uri Dayan, Idan Rozenberg, Yoram Salant
  • Publication number: 20130121599
    Abstract: Various embodiments provide approaches for measuring the rendering times of a webpage that can be browser-independent. In at least some embodiments, as a web page is rendered, video data of the webpage is captured and analyzed to ascertain when the webpage, or portions thereof, have likely been completely rendered. In at least some embodiments, image processing can be performed on captured video data to ascertain, from observed pixel changes over time, when the webpage has likely been rendered.
    Type: Application
    Filed: November 16, 2011
    Publication date: May 16, 2013
    Applicant: Microsoft Corporation
    Inventors: Meir Shmouely, Omer Rosenbaum, Gregory Bershansky, Yuval Peled, M. David Fields, Cenk Ergan, Michael D. Decker, Aaron Rodriguez Hernandez, Matthew P. Kotsenas, Jason J. Weber, Yi Ming Zhou, Kieran Chin Cheong, Kelly Laurence Ford
  • Patent number: 8266414
    Abstract: A method for managing a hardware instruction loop, the method includes: (i) detecting, by a branch prediction unit, an instruction loop; wherein a size of the instruction loop exceeds a size of a storage space allocated in a fetch unit for storing fetched instructions; (ii) requesting from the fetch unit to fetch instructions of the instruction loop that follow the first instructions of the instruction loop; and (iii) selecting, during iterations of the instruction loop, whether to provide to a dispatch unit one of the first instructions of the instruction loop or another instruction that is fetched by the fetch unit; wherein the first instructions of the instruction loop are stored at the dispatch unit.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: September 11, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Lev Vaskevich, Itzhak Barak, Amir Paran, Yuval Peled, Idan Rozenberg, Doron Schupper
  • Publication number: 20100049958
    Abstract: A method for managing a hardware instruction loop, the method includes: (i) detecting, by a branch prediction unit, an instruction loop; wherein a size of the instruction loop exceeds a size of a storage space allocated in a fetch unit for storing fetched instructions; (ii) requesting from the fetch unit to fetch instructions of the instruction loop that follow the first instructions of the instruction loop; and (iii) selecting, during iterations of the instruction loop, whether to provide to a dispatch unit one of the first instructions of the instruction loop or another instruction that is fetched by the fetch unit; wherein the first instructions of the instruction loop are stored at the dispatch unit.
    Type: Application
    Filed: August 19, 2008
    Publication date: February 25, 2010
    Inventors: Lev Vaskevich, Itzhak Barak, Amir Paran, Yuval Peled, Idan Rozenberg, Doron Schupper
  • Publication number: 20100042811
    Abstract: A method for managing branch instructions, the method includes: providing, to pipeline stages of a processor, multiple variable length groups of instructions; wherein each pipeline stage executes a group of instruction during a single execution cycle; receiving, at a certain execution cycle, multiple instruction fetch requests from multiple pipeline stages, each pipeline stage that generates an instruction fetch request stores a variable length group of instructions that comprises a branch instruction; sending to the fetch unit an instruction fetch command that is responsive to a first in order branch instruction in the pipeline stages; wherein if the first in order fetch command is a conditional fetch command then the instruction fetch command comprises a resolved target address; wherein the sending of the instruction fetch command is restricted to a single instruction fetch command per a single execution cycle.
    Type: Application
    Filed: August 12, 2008
    Publication date: February 18, 2010
    Inventors: Yuval Peled, Itzhak Barak, Uri Dayan, Idan Rozenberg, Yoram Salant