Abstract: The present disclosure generally relates to improving programming to data storage devices, such as solid state drives (SSDs). A first memory device has a first XOR element and a second memory device has a second XOR element. The ratio of the first XOR element to the capacity of the first memory device is substantially smaller than the ratio of the second XOR element to the capacity of the second memory device. A read verify operation to find program failures is executed on either a wordline to wordline basis, an erase block to erase block basis, or both a wordline to wordline basis and an erase block to erase block basis. Because the program failures are found and fixed prior to programming to the second memory device, the second XOR element may be decreased substantially.

Abstract: The present disclosure generally relates to improving programming to data storage devices, such as solid state drives (SSDs). A first memory device has a first XOR element and a second memory device has a second XOR element. The ratio of the first XOR element to the capacity of the first memory device is substantially smaller than the ratio of the second XOR element to the capacity of the second memory device. A read verify operation to find program failures is executed on either a wordline to wordline basis, an erase block to erase block basis, or both a wordline to wordline basis and an erase block to erase block basis. Because the program failures are found and fixed prior to programming to the second memory device, the second XOR element may be decreased substantially.

Abstract: A current-balanced voltage source may include two regulated voltage sources, each having an input and an output, and an amplifier to receive a control voltage at a positive input and a feedback voltage at a negative input. The output of each amplifier is coupled to the input of the respective regulated voltage source. The outputs of the regulated voltage sources are coupled together to source a current to a load. A differential amplifier may include positive and negative differential inputs, and positive and negative differential outputs. The positive differential input is coupled to the output of the first regulated voltage source and the negative differential input is coupled to the output of the second regulated voltage source. The positive differential output provides the feedback to the first regulated voltage source, and the negative differential output provides the feedback to the second regulated voltage source.

Abstract: A data storage device includes one or more memory devices that each includes one or more superblocks and a controller coupled to the one or more memory devices. Each superblock includes a plurality of wordlines. The controller is configured to write data to a first wordline of the plurality of wordlines, write data to a second wordline of the plurality of wordlines, perform a read verify operation on the first wordline, and perform a read verify operation on the second wordline. At least one of the first wordline and the second wordline does not include an XOR parity element and one or more wordlines of the plurality of wordlines includes the XOR parity element.

Abstract: The present disclosure generally relates to improving programming to data storage devices, such as solid state drives (SSDs). A first memory device has a first XOR element and a second memory device has a second XOR element. The ratio of the first XOR element to the capacity of the first memory device is substantially smaller than the ratio of the second XOR element to the capacity of the second memory device. A read verify operation to find program failures is executed on either a wordline to wordline basis, an erase block to erase block basis, or both a wordline to wordline basis and an erase block to erase block basis. Because the program failures are found and fixed prior to programming to the second memory device, the second XOR element may be decreased substantially.

Abstract: The present disclosure generally relates to improving programming to data storage devices, such as solid state drives (SSDs). A first memory device has a first XOR element and a second memory device has a second XOR element. The ratio of the first XOR element to the capacity of the first memory device is substantially smaller than the ratio of the second XOR element to the capacity of the second memory device. A read verify operation to find program failures is executed on either a wordline to wordline basis, an erase block to erase block basis, or both a wordline to wordline basis and an erase block to erase block basis. Because the program failures are found and fixed prior to programming to the second memory device, the second XOR element may be decreased substantially.

Abstract: A display system is described that extends the functionality of a mobile display device such that video content generated thereby can be displayed by a different display device, wherein such video content may be the same as or different from video content currently being displayed by the mobile display device. This may be achieved when the mobile display device is engaged with a docking station that provides one or more of power, an extended user interface, network connectivity, and audio/video output features to the mobile display device. Such docking station may include a video interface for connecting the docking station to the different display device. When the mobile display device is engaged with the docking station and the docking station is connected to the different display device via the video interface, video content can be routed from the mobile display device to the different display device.

Abstract: An electronic device includes a housing, a printed circuit board, a first heat sink and a second heat sink. The printed circuit board is disposed internal to the housing and supports at least one integrated circuit (IC) chip. The first heat sink is also disposed internal to the housing and is thermally connected to the at least one IC chip. The second heat sink is connected to the housing such that at least a portion thereof is externally disposed to the housing. The second heat sink is thermally connected to the first heat sink via an aperture in the housing.

Abstract: An electronic device includes a housing, a printed circuit board, a first heat sink and a second heat sink. The printed circuit board is disposed internal to the housing and supports at least one integrated circuit (IC) chip. The first heat sink is also disposed internal to the housing and is thermally connected to the at least one IC chip. The second heat sink is connected to the housing such that at least a portion thereof is externally disposed to the housing. The second heat sink is thermally connected to the first heat sink via an aperture in the housing.

Abstract: In an optical transmitter, continuous wave light from a laser passes through a data modulator (DM) for non-return-to-zero (NRZ) encoding of a data stream and through a pulse modulator to add return-to-zero encoding to the modulated optical signal. A modulator controller monitors the output optical signal power, optimizes the bias setting for the DM and the PM, and optimizes the phase relationship between the pulse and data components of the modulated optical signal. For each optimization, a low amplitude and low frequency dither signal is injected at appropriate points in the modulator. A single photo detector and electrical receiver are used in a multiplexed fashion to monitor the optical output signal and derive separate feedback signals. Remaining control circuitry forces a null in a respective residual dither component in the optical output signal to maintain the desired bias level or phase alignment.

Abstract: In an optical transmitter, continuous wave light from a laser passes through a data modulator (DM) for non-return-to-zero (NRZ) encoding of a data stream and through a pulse modulator to add return-to-zero encoding to the modulated optical signal. A modulator controller monitors the output optical signal power, optimizes the bias setting for the DM and the PM, and optimizes the phase relationship between the pulse and data components of the modulated optical signal. For each optimization, a low amplitude and low frequency dither signal is injected at appropriate points in the modulator. A single photo detector and electrical receiver are used in a multiplexed fashion to monitor the optical output signal and derive separate feedback signals. Remaining control circuitry forces a null in a respective residual dither component in the optical output signal to maintain the desired bias level or phase alignment.

Abstract: A local net area network, or LAN, configuration is provided with a multiple generic LAN channel architecture which can be logically and dynamically changed. The configuration control can be applied to each module of the network and to each port of a module of a LAN hub. The architecture provides multiple LAN protocols to be used simultaneously, as needed, through protocol specific functions. Industry standard protocol such as: token bus, token ring, and fiber distributed data interface (FDDI), can be implemented using the generic channel architecture and its characteristics providing respective network functions. The architecture also provides a digital collision detection method and provides information necessary for precise network statistics monitoring. The token passing ring architecture provides a logical ring formation within the generic channel. A token passing bus architecture uses modified Ethernet.TM.

Abstract: A local net area network, or LAN, configuration is provided with a multiple generic LAN channel architecture which can be logically and dynamically changed. The configuration control can be applied to each module of the network and to each port of a module of a LAN hub. The architecture provides multiple LAN protocols to be used simultaneously, as needed, through protocol specific functions. Industry standard protocol such as: token bus, token ring, and fiber distributed data interface (FDDI), can be implemented using the generic channel architecture and its characteristics providing respective network functions. The architecture also provides a digital collision detection method and provides information necessary for precise network statistics monitoring. The token passing ring architecture provides a logical ring formation within the generic channel. A token passing bus architecture uses modified Ethernet.TM.

Abstract: Jitter is measured by applying a first clock signal to a device-under-test, measuring the phase difference between the jittered clock signal received from the device-under-test and a reference clock signal, and converting the phase difference to a jitter measurement. The phase difference is measured by counting the number of high frequency clock pulses between a transition of the jittered clock signal and a transition of the reference clock signal. The phase difference is converted to a jitter measurement by determining the highest and lowest phase difference count and taking the difference between the highest and lowest count. The phase of the reference clock signal can be adjusted as a function of the highest and lowest count by determined the mean value of the highest and lowest count and adjusting the reference clock to be of this mean value.