Patents by Inventor Yuval YOSKOVITS

Yuval YOSKOVITS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230353356
    Abstract: A storage device includes multiple memory dies and a controller configured to: (i) encrypt a data block using a key schedule that includes a plurality of round keys generated from an encryption key, the encrypting resulting in an encrypted data block; (ii) during the encrypting, modify a key register during a first plurality of iterations, the key register being updated to a final state of the key register after a final iteration of the plurality of iterations; (iii) store the final state of the key register as a decryption key; and (iv) decrypt the encrypted data block using another key schedule that includes the plurality of round keys that are generated using the decryption key during a second plurality of iterations.
    Type: Application
    Filed: April 29, 2022
    Publication date: November 2, 2023
    Inventors: Yan Dumchin, Tzvi Alon, Yuval Yoskovits
  • Patent number: 11704027
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to decode data from the memory device, store a decoder level for the decoded data in a bloom filter, receive a read command for the data, and decode the data using a decoder associated with the stored decoder level. The decoder level corresponds to a decoder having a certain decoding strength. The decoder level is stored in the bloom filter as an ID, where a bloom filter may be associated with each decoder level.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: July 18, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yuval Yoskovits, Yan Dumchin
  • Patent number: 11687405
    Abstract: A data storage device includes two or more memory devices and a controller coupled to the two or more memory devices. The controller is configured to program data to one or more memory devices of the two or more memory devices, select one or more of the one or more memory devices to have additional ECC for the data of the one or more memory devices, program the additional ECC to a first memory device. The data is programmed with error correction code (ECC). The first memory device is distinct from the one or more memory devices. The first memory device is disposed in a central module, where the central module includes additional decoding capability. The additional ECC and the corresponding data with ECC are concatenated and decoded for additional error correction capability.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: June 27, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yuval Yoskovits, Yan Dumchin, Ishai Ilani
  • Publication number: 20230168964
    Abstract: A data storage device includes two or more memory devices and a controller coupled to the two or more memory devices. The controller is configured to program data to one or more memory devices of the two or more memory devices, select one or more of the one or more memory devices to have additional ECC for the data of the one or more memory devices, program the additional ECC to a first memory device. The data is programmed with error correction code (ECC). The first memory device is distinct from the one or more memory devices. The first memory device is disposed in a central module, where the central module includes additional decoding capability. The additional ECC and the corresponding data with ECC are concatenated and decoded for additional error correction capability.
    Type: Application
    Filed: December 1, 2021
    Publication date: June 1, 2023
    Inventors: Yuval Yoskovits, Yan Dumchin, Ishai Ilani
  • Publication number: 20230155608
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to decode data from the memory device, store a decoder level for the decoded data in a bloom filter, receive a read command for the data, and decode the data using a decoder associated with the stored decoder level. The decoder level corresponds to a decoder having a certain decoding strength. The decoder level is stored in the bloom filter as an ID, where a bloom filter may be associated with each decoder level.
    Type: Application
    Filed: November 12, 2021
    Publication date: May 18, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Yuval YOSKOVITS, Yan DUMCHIN
  • Patent number: 11301153
    Abstract: A method and device for out-of-order cryptographic processing to eliminate or ameliorate data dependency stalls, in the cryptographic pipeline of a data storage device, resulting from the application of cipher text stealing. A cryptographic processing pipeline performs the steps of: a) cryptographically process a penultimate data block, to produce a penultimate processed data block, and store a portion of the penultimate processed data block in the memory store; b) cryptographically process at least one leading data block, to produce at least one processed leading data block; and c) cryptographically process a concatenation of a last data block and the portion of the penultimate processed data block, to produce a last processed data block, wherein the cryptographic processing pipeline starts to perform step b) before completing step a).
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: April 12, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amir Segev, Yuval Yoskovits, Shay Benisty
  • Publication number: 20210389875
    Abstract: A method and device for out-of-order cryptographic processing to eliminate or ameliorate data dependency stalls, in the cryptographic pipeline of a data storage device, resulting from the application of cipher text stealing. A cryptographic processing pipeline performs the steps of: a) cryptographically process a penultimate data block, to produce a penultimate processed data block, and store a portion of the penultimate processed data block in the memory store; b) cryptographically process at least one leading data block, to produce at least one processed leading data block; and c) cryptographically process a concatenation of a last data block and the portion of the penultimate processed data block, to produce a last processed data block, wherein the cryptographic processing pipeline starts to perform step b) before completing step a).
    Type: Application
    Filed: June 12, 2020
    Publication date: December 16, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Amir SEGEV, Yuval YOSKOVITS, Shay BENISTY