Abstract: A synchronizer can include a symbol estimator, an inner-pattern de-mapper, a timing tracker, and a correlator. The symbol estimator can be configured to estimate one or more symbols of a received signal based on a phase signal. The inner-pattern de-mapper can be configured to de-map the one or more symbols to generate an inner-pattern de-mapped symbol estimation. The timing tracker can be configured to accumulate the inner-pattern de-mapped symbol estimation and to determine a peak position based on the accumulated inner-pattern de-mapped symbol estimation. The correlator can be configured to correlate the accumulated inner-pattern de-mapped symbol estimation based on a reference signal. The correlation of the accumulated inner-pattern de-mapped symbol estimation can be independent of a signal over sampling rate (OSR). The synchronizer can be adapted in a long range Bluetooth low energy (BLE) receiver.

Abstract: A method and an electronic device for video content recommendation are disclosed.

Abstract: A trellis coded modulator and method for generating an encoded word from an input word. The TCM has a first logic branch configured to generate a data portion of the encoded word; and a second logic branch, coupled in parallel with the first logic branch, and configured to generate a corresponding parity portion of the encoded word sequentially after the generation of the data portion of the encoded word.

Abstract: A trellis coded modulator and method for generating an encoded word from an input word. The TCM has a first logic branch configured to generate a data portion of the encoded word; and a second logic branch, coupled in parallel with the first logic branch, and configured to generate a corresponding parity portion of the encoded word sequentially after the generation of the data portion of the encoded word.

Abstract: A decision feedback equalizer is configured to equalize an input signal to generate a recovered output signal. Linear feed-forward filter circuitry is configured to provide a linearly filtered output signal based on the input signal. Composite trellis decoder circuitry configured to process a combined signal that is based on a combination of at least the linearly feed-forward filtered output signal and on output of linear or non-linear feedback filter circuitry, in accordance with state metrics generated by processing a composite trellis diagram relative to the combined signal, to provide a trellis-decoded output signal as input to the linear or non-linear feedback filter circuitry. The composite trellis decoder circuitry is further configured to provide a particular phase output of the combined signal, based on the state metrics, as the decoded output signal.

Abstract: A decoding system decodes forward error correction (FEC) encoded data. Factor graph circuitry (such as trellis decoder circuitry) processes the FEC encoded data according to at least one factor graph. Order restoring circuitry (such as convolutional deinterleaver circuitry) is coupled to an output of the factor graph circuitry and restores ordering of symbols in the encoded data. Error detection and correction circuitry is coupled to an output of the order restoring circuitry and processes block-based error correcting codes to detect and correct errors in the FEC encoded data and to provide a hard-decision output to an output of the decoding system. Feedback circuitry (such as convolutional interleaver circuitry and symbol interleaver circuitry) is coupled to process the hard-decision output from the error correction and detection circuitry and to provide the processed hard-decision output to the factor graph circuitry.

Abstract: A decoding system decodes forward error correction (FEC) encoded data. Factor graph circuitry (such as trellis decoder circuitry) processes the FEC encoded data according to at least one factor graph. Order restoring circuitry (such as convolutional deinterleaver circuitry) is coupled to an output of the factor graph circuitry and restores ordering of symbols in the encoded data. Error detection and correction circuitry is coupled to an output of the order restoring circuitry and processes block-based error correcting codes to detect and correct errors in the FEC encoded data and to provide a hard-decision output to an output of the decoding system. Feedback circuitry (such as convolutional interleaver circuitry and symbol interleaver circuitry) is coupled to process the hard-decision output from the error correction and detection circuitry and to provide the processed hard-decision output to the factor graph circuitry.

Abstract: A decision feedback equalizer is configured to equalize an input signal to generate a recovered output signal. Linear feed-forward filter circuitry is configured to provide a linearly filtered output signal based on the input signal. Composite trellis decoder circuitry configured to process a combined signal that is based on a combination of at least the linearly feed-forward filtered output signal and on output of linear or non-linear feedback filter circuitry, in accordance with state metrics generated by processing a composite trellis diagram relative to the combined signal, to provide a trellis-decoded output signal as input to the linear or non-linear feedback filter circuitry. The composite trellis decoder circuitry is further configured to provide a particular phase output of the combined signal, based on the state metrics, as the decoded output signal.