Abstract: An array substrate is provided. The array substrate includes a first semiconductor material layer and a second semiconductor material layer on a side of the first semiconductor material layer away from a base substrate. The first semiconductor material layer includes at least active layers of the driving transistor and the data write transistor. The second semiconductor material layer includes at least an active layer of the compensating transistor. A first capacitance is at least partially formed between a gate connecting pad and at least one of the second semiconductor material layer or a first node connecting line. A second capacitance is formed between the first node connecting line and a respective second gate line. The first capacitance is greater than the second capacitance.