Abstract: Disclosed is a use of ethyl p-methoxycinnamate and derivatives thereof in preparing drugs, culture media, regulating agents or cosmetic and skin caring products for maintaining self-renewal and pluripotency of stem cells. The stem cells comprise adult stem cells, embryonic stem cells and induced pluripotent stem (iPS) cells. Also disclosed is a use of ethyl p-methoxycinnamate and the derivatives thereof in in-vitro amplification of stem cells and preparation of induced pluripotent stem (iPS) cells and a use of ethyl p-methoxycinnamate and the derivatives thereof in preparing drugs for treating cell deletion or injury diseases.

Abstract: In various embodiments, an illumination device features an ultraviolet (UV) light-emitting device at least partially surrounded by an encapsulant. A barrier layer is disposed between the light-emitting device and the encapsulant and is configured to substantially prevent UV light emitted by the light-emitting device from entering the encapsulant.

Abstract: In various embodiments, an illumination device features an ultraviolet (UV) light-emitting device at least partially surrounded by an encapsulant and having a rigid lens. Downward forces is applied while the encapsulant is at least partially cured to substantially prevent partial or full detachment of the rigid lens from the light-emitting device, and/or substantially suppress formation of bubbles between the light-emitting device and the rigid lens.

Abstract: In various embodiments, an illumination device features an ultraviolet (UV) light-emitting device at least partially surrounded by an encapsulant. A barrier layer is disposed between the light-emitting device and the encapsulant and is configured to substantially prevent UV light emitted by the light-emitting device from entering the encapsulant.

Abstract: In various embodiments, an illumination device features an ultraviolet (UV) light-emitting device at least partially surrounded by an encapsulant. A barrier layer is disposed between the light-emitting device and the encapsulant and is configured to substantially prevent UV light emitted by the light-emitting device from entering the encapsulant.

Abstract: In various embodiments, an illumination device features an ultraviolet (UV) light-emitting device at least partially surrounded by an encapsulant. A barrier layer is disposed between the light-emitting device and the encapsulant and is configured to substantially prevent UV light emitted by the light-emitting device from entering the encapsulant.

Abstract: The present invention provides a multiple gate transistor architecture that provides an accessible inner source-drain (SD) node. The transistor architecture includes a source structure having multiple source fingers, which extend from a source bus, and a drain structure having multiple drain fingers, which extend from a drain bus. The fingers of the respective source and drain structures are interleaved wherein a meandering path is formed between the source and drain structures. Two or more gate structures run substantially parallel to one another along the meandering path between the source and drain structures. An SD structure is provided between each adjacent pair of gate structures and runs along the meandering path to form the SD node. An SD extension is coupled to the SD structure and accessible by other circuitry to allow a signal to be applied to the SD structure during operation.

Abstract: A method includes generating, from a representation of a first integrated circuit, a representation of a second integrated circuit. The representation of the first integrated circuit includes a plurality of representations of operative memory channel interfaces including a representation of a first operative memory channel physical interface. The representation of the second integrated circuit includes a representation of a pseudo-memory channel physical interface and at least a representation of a second operative memory channel physical interface. The generating includes replacing an instantiation of a first circuit of the representation of the first operative memory channel physical interface with an instantiation of a second circuit. The instantiation of the second circuit is a representation of a circuit that is logically equivalent to a first circuit represented by the instantiation of the first circuit.

Abstract: A method includes generating, from a representation of a first integrated circuit, a representation of a second integrated circuit. The representation of the first integrated circuit includes a plurality of representations of operative memory channel interfaces including a representation of a first operative memory channel physical interface. The representation of the second integrated circuit includes a representation of a pseudo-memory channel physical interface and at least a representation of a second operative memory channel physical interface. The generating includes replacing an instantiation of a first circuit of the representation of the first operative memory channel physical interface with an instantiation of a second circuit. The instantiation of the second circuit is a representation of a circuit that is logically equivalent to a first circuit represented by the instantiation of the first circuit.

Abstract: An inventive isolated converter which exempts the auxiliary isolation devices with accurate voltage regulation is disclosed. The converter includes the primary side circuit with a primary controller controlling the on and off of the primary switch and a secondary side circuit with a secondary controller controlling the on and off of the secondary synchronous rectifier. The isolated converter uses the secondary controller to turn on the secondary synchronous rectifier after the secondary current decreases to zero to generate a negative tail current and turns off the secondary synchronous rectifier at a reference tail current peak value to generate a reflected negative current at the primary side circuit for turning on the primary switch.

Abstract: The present invention provides a multiple gate transistor architecture that provides an accessible inner source-drain (SD) node. The transistor architecture includes a source structure having multiple source fingers, which extend from a source bus, and a drain structure having multiple drain fingers, which extend from a drain bus. The fingers of the respective source and drain structures are interleaved wherein a meandering path is formed between the source and drain structures. Two or more gate structures run substantially parallel to one another along the meandering path between the source and drain structures. An SD structure is provided between each adjacent pair of gate structures and runs along the meandering path to form the SD node. An SD extension is coupled to the SD structure and accessible by other circuitry to allow a signal to be applied to the SD structure during operation.

Abstract: The present invention relates to an electrostatic discharge (ESD) clamp circuit that is used to protect other circuitry from high voltage ESD events. The ESD clamp circuit may include a field effect transistor (FET) element as a clamping element, which is triggered by using a drain-to-gate capacitance, a drain-to-gate resistance, or both of the FET element, and a resistive element as a voltage divider to divide down an ESD voltage to provide a triggering gate voltage of the FET element. In its simplest embodiment, the ESD clamp circuit includes only an FET element and a resistive element. Therefore, the single FET element ESD clamp circuit may be small compared to other ESD protection circuits. The simplicity of the ESD clamp circuit may minimize parasitic capacitances, thereby maximizing linearity of the ESD clamp circuit over a wide frequency range.

Abstract: The present invention relates to an electrostatic discharge (ESD) clamp circuit that is used to protect other circuitry from high voltage ESD events. The ESD clamp circuit may include a field effect transistor (FET) element as a clamping element, which is triggered by using a drain-to-gate capacitance and a drain-to-gate resistance of the FET element and a resistive element as a voltage divider to divide down an ESD voltage to provide a triggering gate voltage of the FET element. In its simplest embodiment, the ESD clamp circuit includes only an FET element, a resistive element, a source-coupled level shifting diode, and a reverse protection diode. Therefore, the ESD clamp circuit may be small compared to other ESD protection circuits. The simplicity of the ESD clamp circuit may minimize parasitic capacitances, thereby maximizing linearity of the ESD clamp circuit over a wide frequency range.

Abstract: An inventive isolated converter which exempts the auxiliary isolation devices with accurate voltage regulation is disclosed. The converter includes the primary side circuit with a primary controller controlling the on and off of the primary switch and a secondary side circuit with a secondary controller controlling the on and off of the secondary synchronous rectifier. The isolated converter uses the secondary controller to turn on the secondary synchronous rectifier after the secondary current decreases to zero to generate a negative tail current and turns off the secondary synchronous rectifier at a reference tail current peak value to generate a reflected negative current at the primary side circuit for turning on the primary switch.

Abstract: A timing circuit operates by applying an arbitrary voltage across a resistance, and using the resulting current to generate a charging current which charges and/or discharges a capacitance to an endpoint voltage. Additional circuitry is arranged such that the capacitance is charged and/or discharged until its voltage crosses a threshold which is proportional to one of the resistance's endpoint voltages, such that the capacitance's endpoint voltage tracks the resistance's endpoint voltage. Thus, the resistor voltage can vary with supply voltage or temperature, or the resistance value itself can vary, without materially affecting the timing relationships. The arbitrary voltage is preferably provided with a pair of diode-connected transistors connected in series with the resistance, so that a single transistor operated at the same current density as one of the diode-connected transistors establishes the threshold voltage and detects when the capacitor voltage reaches the threshold.

Abstract: A timing circuit operates by applying an arbitrary voltage across a resistance, and using the resulting current to generate a charging current which charges and/or discharges a capacitance to an endpoint voltage. Additional circuitry is arranged such that the capacitance is charged and/or discharged until its voltage crosses a threshold which is proportional to one of the resistance's endpoint voltages, such that the capacitance's endpoint voltage tracks the resistance's endpoint voltage. Thus, the resistor voltage can vary with supply voltage or temperature, or the resistance value itself can vary, without materially affecting the timing relationships. The arbitrary voltage is preferably provided with a pair of diode-connected transistors connected in series with the resistance, so that a single transistor operated at the same current density as one of the diode-connected transistors establishes the threshold voltage and detects when the capacitor voltage reaches the threshold.

Abstract: A switched noise filter circuit for DC-DC converters which use the instantaneous output voltage to establish the converter's duty ratio. The converter cycles the switching element on and off for time intervals Ton and Toff, respectively. A switching control circuit includes a filter capacitance connected between the feedback node and ground, and a comparator which compares a feedback voltage Vfb with a fixed voltage Vref; at least one of Ton and Toff is a “modulated” interval which is terminated when Vfb crosses Vref due to the discharge of the filter capacitance. A switched noise filter circuit applies an offset voltage to Vfb during at least one of Ton, and Toff, with the offset voltage disconnected from Vfb by the beginning of the modulated interval or shortly thereafter. When the offset voltage is properly applied, the effect of extraneous electromagnetic noise coupled into Vfb is reduced.

Abstract: A switched noise filter circuit for DC-DC converters which use the instantaneous output voltage to establish the converter's duty ratio. The converter cycles the switching element on and off for time intervals Ton and Toff, respectively. A switching control circuit includes a filter capacitance connected between the feedback node and ground, and a comparator which compares a feedback voltage Vfb with a fixed voltage Vref; at least one of Ton and Toff is a “modulated” interval which is terminated when Vfb crosses Vref due to the discharge of the filter capacitance. A switched noise filter circuit applies an offset voltage to Vfb during at least one of Ton and Toff, with the offset voltage disconnected from Vfb by the beginning of the modulated interval or shortly thereafter. When the offset voltage is properly applied, the effect of extraneous electromagnetic noise coupled into Vfb is reduced.

Abstract: A gate-controlled switch includes a gate turn-off thyristor in series with a diode. By using the diode in series with the GTO, the switch significantly increases the turn-off voltage that can be used for the current commutation. The unity turn-off gain and the snubberless turn-off capability are demonstrated.