Abstract: A field plate electrode is formed in an inside of a trench via a first insulating film. Another part of the field plate electrode is selectively removed such that part of the field plate electrode is left as a lead portion. After the first insulating film is recessed, a protective film is formed on the first insulating film. A gate insulating film is formed in the inside of the trench, and a second insulating film is formed so as to cover the field plate electrode. A conductive film is formed on the gate insulating, second insulating film and protective films. A gate electrode is formed on the field plate electrode by removing the conductive film located in an outside of the trench. At this time, the conductive film formed on each of the protective film and the second insulating film, which are in contact with the lead portion, is removed.

Abstract: Reliability of a semiconductor device is improved. A field plate electrode is formed on an insulating film inside a trench. Next, by an isotropic etching process to the insulating film, the insulating film is thinned, and an upper portion of the field plate electrode is exposed from the insulating film. Next, an isotropic etching process (chemical dry etching process) is performed to the field plate electrode exposed from the insulating film. In this manner, a corner of the upper portion of the field plate electrode is chamfered or rounded, and therefore, a concentration of electric field at the upper portion of the field plate electrode can be moderated.

Abstract: A trench is formed in a semiconductor substrate. A first silicon oxide film is formed in an inside of the trench. A poly-crystalline silicon film is formed on the first silicon oxide film. A second silicon oxide film is formed from the poly-crystalline silicon film by performing a thermal oxidation treatment to the poly-crystalline silicon film. Thus, an insulating film including the first silicon oxide film and the second silicon oxide film is formed. A first conductive film is formed so as to embed the inside of the trench via the insulating film.

Abstract: A trench is formed in a semiconductor substrate. A first silicon oxide film is formed in an inside of the trench. A poly-crystalline silicon film is formed on the first silicon oxide film. A second silicon oxide film is formed from the poly-crystalline silicon film by performing a thermal oxidation treatment to the poly-crystalline silicon film. Thus, an insulating film including the first silicon oxide film and the second silicon oxide film is formed. A first conductive film is formed so as to embed the inside of the trench via the insulating film.

Abstract: A trench is formed in a semiconductor substrate. An insulating film is formed in the trench and on an upper surface of the semiconductor substrate. An ion implantation is performed to the insulating film. An etching treatment is performed to the insulating film, thereby a thickness of the insulating film is reduced. A conductive film is formed in the trench via the insulating film. In plan view, the trench extends in a Y-direction. The above-described ion implantation is performed from a direction inclined by a predetermined angle from an extending direction of a normal line with respect to the upper surface of the semiconductor substrate.

Abstract: An improved power MOSFET of a split gate structure including a gate electrode and a field plate electrode in a trench is disclosed. The improved power MOSFET includes a field plate electrode FP formed at a lower portion of a trench TR and a gate electrode GE formed an upper portion of the trench TR. The field plate electrode FP further includes a contact portion FPa which is formed at the upper portion of the trench TR to provide a source potential. The gate electrode GE further includes a connecting portion GEa at the both sides of the contact portion FPa in the trench TR. The connecting portion GEa electrically connects between one portion of the gate electrode GE at a region 2A side and the other portion of the gate electrode GE at a region 2A? side.

Abstract: Disclosed is a technique for improving performance of a semiconductor device having a trench gate type power MOSFET. Concretely, a method of manufacturing a semiconductor device having a trench gate type power MOSFET comprising: forming a trench in a semiconductor substrate; introducing both of a p-type impurity(Boron) and carbon (C) into a bottom surface of the trench to form a p-type impurity introduced region; forming a gate electrode to fill the trench; forming a channel forming region and a source region at the side of the trench in which the gate electrode is filled; and subjecting a heat treatment to the p-type impurity introduced region to form an electric field relaxation layer having suppressed crystal defects and a controlled shape.

Abstract: In a vertical power MOSFET having a superjunction structure, the withstand voltage of the power MOSFET can be ensured even if the aspect ratios of an n-type column region and a p-type column region are increased so as to vary the impurity concentration of the p-type column region. P-type semiconductor regions PR1 are formed on the sides of an n-type column NC1 adjacent to a p-type column region PC1. In this configuration, the p-type semiconductor region PR1 is formed from the upper end of the n-type column region NC1 to about a half depth of a height from the upper end to the lower end of the side of the n-type column region NC1. This inclines the sides of the overall p-type column region including the p-type semiconductor regions PR1 and the p-type column region PC1.

Abstract: Properties of a semiconductor device are improved. A semiconductor device having a superjunction structure, in which p-type column regions and n-type column regions are periodically arranged, is configured as follows. Each n-type column region has a vertical section including an n-type epitaxial layer located between trenches and a tapered embedded n-type epitaxial film disposed on a side face of the trench. Each p-type column region includes an embedded p-type epitaxial film disposed within the trench. The tapered embedded n-type epitaxial film is thus provided on the sidewall of the trench in which the p-type column region is to be disposed, thereby the p-type column region is allowed to have an inverted trapezoidal shape, leading to an increase in margin for a variation in concentration of a p-type impurity in the p-type column region. On resistance can be reduced by lateral diffusion of an n-type impurity (for example, As).

Abstract: In a vertical power MOSFET having a superjunction structure, the withstand voltage of the power MOSFET can be ensured even if the aspect ratios of an n-type column region and a p-type column region are increased so as to vary the impurity concentration of the p-type column region. P-type semiconductor regions PR1 are formed on the sides of an n-type column NC1 adjacent to a p-type column region PC1. In this configuration, the p-type semiconductor region PR1 is formed from the upper end of the n-type column region NC1 to about a half depth of a height from the upper end to the lower end of the side of the n-type column region NC1. This inclines the sides of the overall p-type column region including the p-type semiconductor regions PR1 and the p-type column region PC1.

Abstract: In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).

Abstract: A super junction structure having a high aspect ratio is formed. An epitaxial layer is dividedly formed in layers using the trench fill process, and when each of the layers has been formed, trenches are formed in that layer. For example, when a first epitaxial layer has been formed, first trenches are formed in the epitaxial layer. Subsequently, when a second epitaxial layer has been formed, second trenches are formed in the epitaxial layer. Subsequently, when a third epitaxial layer has been formed, third trenches are formed in the third epitaxial layer.

Abstract: In a vertical power MOSFET having a superjunction structure, the withstand voltage of the power MOSFET can be ensured even if the aspect ratios of an n-type column region and a p-type column region are increased so as to vary the impurity concentration of the p-type column region. P-type semiconductor regions PR1 are formed on the sides of an n-type column NC1 adjacent to a p-type column region PC1. In this configuration, the p-type semiconductor region PR1 is formed from the upper end of the n-type column region NC1 to about a half depth of a height from the upper end to the lower end of the side of the n-type column region NC1. This inclines the sides of the overall p-type column region including the p-type semiconductor regions PR1 and the p-type column region PC1.

Abstract: To provide a semiconductor device including a power semiconductor element having improved reliability. The semiconductor device has a cell region and a peripheral region formed outside the cell region. The n type impurity concentration of n type column regions in the cell region is made higher than that of n type column regions comprised of an epitaxial layer in the peripheral region. Further, a charge balance is kept in each of the cell region and the peripheral region and each total electric charge is set so that a total electric charge of first p type column regions and a total electric charge of n type column regions in the cell region become larger than a total electric charge of third p type column regions and n type column regions comprised of an epitaxial layer in the peripheral region, respectively.

Abstract: Reduction of power consumption of a semiconductor device is aimed. The semiconductor device includes a cell region where a vertical power MOSFET is formed and an intermediate region surrounding the cell region. In each of the cell region and the intermediate region, a plurality of p-type column regions and a plurality of n-type column regions are alternately formed. The n-type column region arranged in the cell region has a defect region formed therein, whereas the n-type column region arranged in the intermediate region does not have the defect region. A defect density in the n-type column region arranged in the cell region is larger than that in the n-type column region arranged in the intermediate region.

Abstract: In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).

Abstract: To provide a semiconductor device including a power semiconductor element having improved reliability. The semiconductor device has a cell region and a peripheral region formed outside the cell region. The n type impurity concentration of n type column regions in the cell region is made higher than that of n type column regions comprised of an epitaxial layer in the peripheral region. Further, a charge balance is kept in each of the cell region and the peripheral region and each total electric charge is set so that a total electric charge of first p type column regions and a total electric charge of n type column regions in the cell region become larger than a total electric charge of third p type column regions and n type column regions comprised of an epitaxial layer in the peripheral region, respectively.

Abstract: Properties of a semiconductor device are improved. A semiconductor device having a superjunction structure, in which p-type column regions and n-type column regions are periodically arranged, is configured as follows. Each n-type column region has a vertical section including an n-type epitaxial layer located between trenches and a tapered embedded n-type epitaxial film disposed on a side face of the trench. Each p-type column region includes an embedded p-type epitaxial film disposed within the trench. The tapered embedded n-type epitaxial film is thus provided on the sidewall of the trench in which the p-type column region is to be disposed, thereby the p-type column region is allowed to have an inverted trapezoidal shape, leading to an increase in margin for a variation in concentration of a p-type impurity in the p-type column region. On resistance can be reduced by lateral diffusion of an n-type impurity (for example, As).

Abstract: In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).

Abstract: A super junction structure having a high aspect ratio is formed. An epitaxial layer is dividedly formed in layers using the trench fill process, and when each of the layers has been formed, trenches are formed in that layer. For example, when a first epitaxial layer has been formed, first trenches are formed in the epitaxial layer. Subsequently, when a second epitaxial layer has been formed, second trenches are formed in the epitaxial layer. Subsequently, when a third epitaxial layer has been formed, third trenches are formed in the third epitaxial layer.