Patents by Inventor Yuya KAKEHASHI

Yuya KAKEHASHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device
    Patent number: 10833673
    Abstract: An operation adjustment method of an SOI device comprises steps of: (a) obtaining a drain current-substrate bias voltage characteristic of an NMOS transistor for a source-gate voltage of 0V; (b) obtaining a lowest substrate bias voltage which turns on the NMOS transistor from the drain current-substrate bias voltage characteristic; (c) determining an upper limit of a substrate bias voltage of a PMOS transistor as a voltage obtained by subtracting a built-in potential of a pn junction from the lowest substrate bias voltage; and (d) determining the substrate bias voltage of the PMOS transistor as a positive voltage lower than the upper limit. Reduction in the power consumption and maintenance of the radiation tolerance are both achieved for the SOI device.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: November 10, 2020
    Assignees: MITSUBISHI HEAVY INDUSTRIES, LTD., JAPAN AEROSPACE EXPLORATION AGENCY
    Inventors: Daisuke Matsuura, Takanori Narita, Masahiro Kato, Daisuke Kobayashi, Kazuyuki Hirose, Osamu Kawasaki, Yuya Kakehashi, Taichi Ito
  • SEMICONDUCTOR DEVICE
    Publication number: 20200007124
    Abstract: An operation adjustment method of an SOI device comprises steps of: (a) obtaining a drain current-substrate bias voltage characteristic of an NMOS transistor for a source-gate voltage of 0V; (b) obtaining a lowest substrate bias voltage which turns on the NMOS transistor from the drain current-substrate bias voltage characteristic; (c) determining an upper limit of a substrate bias voltage of a PMOS transistor as a voltage obtained by subtracting a built-in potential of a pn junction from the lowest substrate bias voltage; and (d) determining the substrate bias voltage of the PMOS transistor as a positive voltage lower than the upper limit. Reduction in the power consumption and maintenance of the radiation tolerance are both achieved for the SOI device.
    Type: Application
    Filed: February 7, 2018
    Publication date: January 2, 2020
    Inventors: Daisuke MATSUURA, Takanori NARITA, Masahiro KATO, Daisuke KOBAYASHI, Kazuyuki HIROSE, Osamu KAWASAKI, Yuya KAKEHASHI, Taichi ITO