Patents by Inventor Yu-Yang Chen

Yu-Yang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11950771
    Abstract: The present invention provides a supporting hook structure, comprising a sleeve, a fixing rod, a first limit unit, a hook and a fixing device. The fixing rod is connected to the side surface of the sleeve. The hook body is connected to one end of the sleeve. The first limit unit is arranged on the side surface of the sleeve and adjacent to the hook body. The first limit unit makes the hook body rotates with the axis direction of the sleeve as a rotation axis. The fixing device is connected to the other end of the sleeve to fix the rotating position of the hook body. Through the above, the hook part enters the proximal thigh from a surgical entrance and the hook part rotates to make the hook part abut against the proximal femur to complete the positioning and fixation of the femur hook structure to the femur.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: April 9, 2024
    Assignee: UNITED ORTHOPEDIC CORPORATION
    Inventors: Yan-Shen Lin, Jiann-Jong Liau, Yu-Liang Liu, Teh-Yang Lin, Wen-Chuan Chen
  • Patent number: 11942358
    Abstract: The present disclosure describes a method of forming low thermal budget dielectrics in semiconductor devices. The method includes forming, on a substrate, first and second fin structures with an opening in between, filling the opening with a flowable isolation material, treating the flowable isolation material with a plasma, and removing a portion of the plasma-treated flowable isolation material between the first and second fin structures.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mrunal Abhijith Khaderbad, Ko-Feng Chen, Zheng-Yong Liang, Chen-Han Wang, De-Yang Chiou, Yu-Yun Peng, Keng-Chu Lin
  • Patent number: 11939603
    Abstract: A modified cutinase is disclosed. The cutinase has the modified amino acid sequence of SEQ ID NO: 2, wherein the modification is a substitution of asparagine at position 181 with alanine, or substitutions of asparagine at position 181 with alanine and phenylalanine at position 235 with leucine. The modified enzyme has improved PET-hydrolytic activity, and thus, the high-activity PET hydrolase is obtained, and the industrial application value of the PET hydrolase is enhanced.
    Type: Grant
    Filed: June 21, 2023
    Date of Patent: March 26, 2024
    Assignee: HUBEI UNIVERSITY
    Inventors: Chun-Chi Chen, Jian-Wen Huang, Jian Min, Xian Li, Beilei Shi, Panpan Shen, Yu Yang, Yumei Hu, Longhai Dai, Lilan Zhang, Yunyun Yang, Rey-Ting Guo
  • Patent number: 11923630
    Abstract: An electrical connector assembly includes: a bracket; and at least one transmission assembly mounted to the bracket and including an internal printed circuit board (PCB), a board-mount connector connected to a first row of conductive pads disposed at a bottom end portion of the PCB, and a plug-in connector connected to a second row of conductive pads disposed at a front end portion of the PCB, wherein the PCB has a third row of conductive pads disposed at a rear end portion thereof.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: March 5, 2024
    Assignees: FUDING PRECISION INDUSTRY (ZHENGZHOU) CO., LTD., FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventors: Shih-Wei Hsiao, Yu-San Hsiao, Yen-Chih Chang, Yu-Ke Chen, Na Yang, Wei-Hua Zhang
  • Patent number: 11916471
    Abstract: An example electronic device includes a controller to determine a user touch detection by a power adaptor coupled to the electronic device to operate the electronic device in an AC power mode. The power adaptor may comprise a proximity sensor to detect a user touch for detachment of the power adaptor from the electronic device, and a control circuit to operate a configuration pin in a low output mode to signal user touch detection. The controller may initiate central processing unit (CPU) throttling to reduce power consumption by the electronic device. The controller may further stop CPU throttling in response to detecting that the power adaptor has been detached from the electronic device. Further, the controller may switch the electronic device to a DC power mode to operate using DC power supplied by a battery of the electronic device in response to power adaptor detachment.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: February 27, 2024
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Ting-Yang Tsai, Yi-Chen Chen, Ching-Lung Wang, Yu-Min Shen
  • Patent number: 11913047
    Abstract: A method for producing ?-aminobutyric acid includes cultivating, in a culture medium containing glutamic acid or a salt thereof, a probiotic composition including at least one lactic acid bacterial strain selected from the group consisting of Bifidobacterium breve CCFM1025 which is deposited at the Guangdong Microbial Culture Collection Center under an accession number GDMCC 60386, Lactobacillus acidophilus TYCA06, Lactobacillus plantarum LPL28, and Bifidobacterium longum subsp. infantis BLI-02 which are deposited at the China General Microbiological Culture Collection Center respectively under accession numbers CGMCC 15210, CGMCC 17954, and CGMCC 15212, Lactobacillus salivarius subsp. salicinius AP-32 which is deposited at the China Center for Type Culture Collection under an accession number CCTCC M 2011127, and combinations thereof.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: February 27, 2024
    Assignee: GLAC BIOTECH CO., LTD.
    Inventors: Hsieh-Hsun Ho, Ching-Wei Chen, Yu-Fen Huang, Chen-Hung Hsu, Wen-Yang Lin, Yi-Wei Kuo, Shin-Yu Tsai
  • Publication number: 20240027185
    Abstract: A method for measuring a thickness of a thin film layer disposed on a piece of glass is implemented using a computer device that stores a thin film image of the thin film layer, a surface dataset associated with a surface of the thin film layer, and a plurality of reference parameter sets each being associated with a specific thickness of the thin film layer, the method including: generating a spectral image dataset that includes spectral data associated with different pixels of the thin film image using a spectral transformation matrix; performing regression analysis on the surface dataset and the spectral image dataset, so as to obtain a thickness parameter set including a plurality of thickness parameters; and determining a thickness of the thin film layer using the thickness parameter set and the plurality of reference parameter sets.
    Type: Application
    Filed: October 27, 2022
    Publication date: January 25, 2024
    Applicant: National Chung Cheng University
    Inventors: Hsiang-Chen Wang, Yu-Yang Chen, Yu-Ming Tsao, Yu-Lin Liu, Ching-Yi Huang
  • Publication number: 20230153107
    Abstract: A data storage device includes a controller, a data storage unit, a microprocessor, and a network communication unit. The controller includes a firmware. The data storage unit includes a first system storage sector and a second system storage sector. The first system storage sector stores an original operating system, and the second system storage sector stores a backup operating system. When the data storage device receives an operating system differential file from a cloud management platform, the firmware updates the backup operating system in the second system storage sector to obtain a new version of backup operating system. Accordingly, the backup operating system of the data storage device can be quickly updated by downloading a small file size of the operating system differential file so as to enhance the convenience for the updating of the backup operating system.
    Type: Application
    Filed: January 18, 2022
    Publication date: May 18, 2023
    Inventor: YU-YANG CHEN
  • Patent number: 10916634
    Abstract: A method of fabricating a semiconductor device includes forming a memory gate and a hard mask layer on the memory gate, forming a select gate on a sidewall of the memory gate and the hard mask layer, performing a selective oxidation process to form an oxide layer on the hard mask layer and the select gate, wherein a portion of the oxide layer on the select gate is thicker than a portion of the oxide layer on the hard mask layer, and removing the oxide layer on the hard mask layer and the hard mask layer to expose a top surface of the memory gate.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: February 9, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei Xu, Wenbo Ding, Yu-Yang Chen, Wang Xiang
  • Publication number: 20200373164
    Abstract: A method of fabricating a semiconductor device includes forming a memory gate and a hard mask layer on the memory gate, forming a select gate on a sidewall of the memory gate and the hard mask layer, performing a selective oxidation process to form an oxide layer on the hard mask layer and the select gate, wherein a portion of the oxide layer on the select gate is thicker than a portion of the oxide layer on the hard mask layer, and removing the oxide layer on the hard mask layer and the hard mask layer to expose a top surface of the memory gate.
    Type: Application
    Filed: May 20, 2019
    Publication date: November 26, 2020
    Inventors: WEI XU, WENBO DING, Yu-Yang Chen, Wang Xiang
  • Patent number: 9852912
    Abstract: A method of manufacturing a semiconductor device includes providing a silicon substrate with multiple layers formed on a front side and a backside, wherein at least a dielectric layer is formed on the backside of the silicon substrate; defining isolation regions and active regions at the front side of the silicon substrate, wherein the active regions are separated by the isolation regions; treating the multiple layers formed at the front side and the backside of the silicon substrate, so as to remain the dielectric layer as an outermost layer exposed at the backside of the silicon substrate; and depositing a polysilicon layer on the isolation regions and the active regions at the front side of the silicon substrate.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: December 26, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Sheng Zhang, Liang Yi, Wen-Bo Ding, Chien-Kee Pang, Yu-Yang Chen
  • Patent number: 9780101
    Abstract: The present invention provides a flash cell structure and a method of fabricating the same. The flash cell structure includes a semiconductor substrate, a stacked gate structure disposed on the semiconductor substrate, a first doped region disposed in the semiconductor substrate at a side of the stacked gate structure, a first dielectric layer, a second dielectric layer, and an erase gate. The stacked gate structure includes a floating gate insulated from the semiconductor substrate and a control gate disposed on the floating gate and insulated from the floating gate. The first dielectric layer is disposed on a sidewall of the floating gate. The second dielectric layer is disposed on the first doped region. A thickness of the first dielectric layer is less than a thickness of the second dielectric layer.
    Type: Grant
    Filed: November 24, 2016
    Date of Patent: October 3, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Sheng Zhang, Wenbo Ding, Xiaofei Han, Chien-Kee Pang, Yu-Yang Chen, Jubao Zhang
  • Publication number: 20140196251
    Abstract: A semiconductor fabricating apparatus includes a reaction chamber, a first gas pipeline, and a second gas pipeline. The first gas pipeline includes a first cleaning gas pipeline for providing a first cleansing gas to the reaction chamber in a cleansing process, and a second cleansing gas pipeline for providing a second cleansing gas to the reaction chamber in the cleansing process. The first cleansing gas pipeline and the second cleansing gas pipeline are connected in parallel. The second gas pipeline provides a reactive gas to the reaction chamber in a fabricating process. The first gas pipeline and the second gas pipeline are connected in parallel.
    Type: Application
    Filed: January 13, 2013
    Publication date: July 17, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: YINGJIE XU, Chaw Che, Yu-Yang Chen, Liang-Yong Tan, HAI YUAN, XIANYU MENG
  • Patent number: 7362835
    Abstract: The present invention discloses a clock generator circuit for generating an output clock signal. The clock generator circuit includes: a random frequency code generator for generating a frequency code randomly, wherein the random frequency code generator is clocked by a first clock signal; an accumulator electrically connected to the random frequency code generator, for generating a selection code by accumulating the frequency code, wherein the accumulator is clocked by the first clock signal; a first multiplexer electrically connected to the accumulator, for selecting one of a plurality of reference clock signals as the first clock signal according to the selection code; and a toggle circuit electrically connected to the first multiplexer, being clocked by the first clock signal for generating the output clock signal.
    Type: Grant
    Filed: February 4, 2005
    Date of Patent: April 22, 2008
    Assignee: Mediatek Incorporation
    Inventor: Yu-Yang Chen
  • Publication number: 20060176940
    Abstract: The present invention discloses a clock generator circuit for generating an output clock signal. The clock generator circuit includes: a random frequency code generator for generating a frequency code randomly, wherein the random frequency code generator is clocked by a first clock signal; an accumulator electrically connected to the random frequency code generator, for generating a selection code by accumulating the frequency code, wherein the accumulator is clocked by the first clock signal; a first multiplexer electrically connected to the accumulator, for selecting one of a plurality of reference clock signals as the first clock signal according to the selection code; and a toggle circuit electrically connected to the first multiplexer, being clocked by the first clock signal for generating the output clock signal.
    Type: Application
    Filed: February 4, 2005
    Publication date: August 10, 2006
    Inventor: Yu-Yang Chen