Patents by Inventor Yuyang Sun
Yuyang Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9171735Abstract: Methods are provided for fabricating semiconductor integrated circuits including isolated trench features. In one embodiment, a method includes providing a semiconductor substrate with an overlying process layer. A trench pattern to be etched into the process layer is determined and that trench pattern is decomposed into first and second patterns, the second pattern including an isolated trench. First and second lithographic masks are formed to implement the first and second patterns, the second mask implementing the second pattern, the isolated trench, and a plurality of density balancer patterns symmetrically positioned with respect to the isolated trench. A first resist layer is patterned with the first lithographic mask and the process layer is etched with the first resist layer. A second resist layer is patterned with the second lithographic mask and the process layer is etched with the second resist layer to implement the required trench pattern in the process layer.Type: GrantFiled: February 15, 2013Date of Patent: October 27, 2015Assignee: GLOBALFOUNDRIES, INC.Inventors: Sohan Mehta, Norman Chen, Yuyang Sun, Matthew Herrick, Shyam Pal, Jeong Soo Kim
-
Patent number: 9064086Abstract: A method includes receiving a design layout file for an integrated circuit device in a computing apparatus. The design layout file specifies dimensions of a plurality of features. The design layout file is decomposed to a plurality of colored layout files, each colored layout file representing a particular reticle in a multiple patterning process. Each of the colored layout files is retargeted separately in the computing apparatus to generate a plurality of retargeted colored layout files. Retargeting each of the colored layout files includes increasing dimensions of a first plurality of features based on spacings between the first plurality of features and adjacent features. The retargeted layout files are combined to generate a combined layout file. Features in the combined layout file are retargeted in the computing apparatus to increase dimensions of a second plurality of features based on spacings between the second plurality of features and adjacent features.Type: GrantFiled: October 28, 2014Date of Patent: June 23, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Yuyang Sun, Chidam Kallingal, Norman Chen
-
Patent number: 8993224Abstract: One illustrative method disclosed herein involves identifying an overall target pattern comprised of at least one hole-type feature, decomposing the overall target pattern into at least a first sub-target pattern and a second sub-target pattern, wherein the first sub-target pattern and the second sub-target pattern each comprise at least one common hole-type feature, generating a first set of mask data information corresponding to the first sub-target pattern, and generating a second set of mask data information corresponding to the second sub-target pattern.Type: GrantFiled: May 23, 2014Date of Patent: March 31, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Yuyang Sun, Norman S. Chen, Jian Liu
-
Publication number: 20150046887Abstract: A method includes receiving a design layout file for an integrated circuit device in a computing apparatus. The design layout file specifies dimensions of a plurality of features. The design layout file is decomposed to a plurality of colored layout files, each colored layout file representing a particular reticle in a multiple patterning process. Each of the colored layout files is retargeted separately in the computing apparatus to generate a plurality of retargeted colored layout files. Retargeting each of the colored layout files includes increasing dimensions of a first plurality of features based on spacings between the first plurality of features and adjacent features. The retargeted layout files are combined to generate a combined layout file. Features in the combined layout file are retargeted in the computing apparatus to increase dimensions of a second plurality of features based on spacings between the second plurality of features and adjacent features.Type: ApplicationFiled: October 28, 2014Publication date: February 12, 2015Inventors: Yuyang Sun, Chidam Kallingal, Norman Chen
-
Publication number: 20150010851Abstract: One illustrative method disclosed herein includes the steps of decomposing an initial overall target exposure pattern into at least a first decomposed sub-target pattern and a second decomposed sub-target pattern, performing first and second retargeting processes on the first and second decomposed sub-target patterns while using the other sub-target pattern as a reference layer, respectively, to thereby define retargeted first and second decomposed sub-target patterns, respectively, and, after performing the first and second retargeting processes, performing at least one process operation to determine if each of the retargeted first decomposed sub-target pattern and the retargeted second decomposed sub-target pattern is in compliance with at least one design rule.Type: ApplicationFiled: July 8, 2013Publication date: January 8, 2015Inventors: Chidambaram G. Kallingal, YuYang Sun
-
Patent number: 8921016Abstract: One illustrative method disclosed herein includes the steps of decomposing an initial overall target exposure pattern into at least a first decomposed sub-target pattern and a second decomposed sub-target pattern, performing first and second retargeting processes on the first and second decomposed sub-target patterns while using the other sub-target pattern as a reference layer, respectively, to thereby define retargeted first and second decomposed sub-target patterns, respectively, and, after performing the first and second retargeting processes, performing at least one process operation to determine if each of the retargeted first decomposed sub-target pattern and the retargeted second decomposed sub-target pattern is in compliance with at least one design rule.Type: GrantFiled: July 8, 2013Date of Patent: December 30, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Chidambaram G. Kallingal, YuYang Sun
-
Patent number: 8910094Abstract: A method includes receiving a design layout file for an integrated circuit device in a computing apparatus. The design layout file specifies dimensions of a plurality of features. The design layout file is decomposed to a plurality of colored layout files, each colored layout file representing a particular reticle in a multiple patterning process. Each of the colored layout files is retargeted separately in the computing apparatus to generate a plurality of retargeted colored layout files. Retargeting each of the colored layout files includes increasing dimensions of a first plurality of features based on spacings between the first plurality of features and adjacent features. The retargeted layout files are combined to generate a combined layout file. Features in the combined layout file are retargeted in the computing apparatus to increase dimensions of a second plurality of features based on spacings between the second plurality of features and adjacent features.Type: GrantFiled: February 6, 2013Date of Patent: December 9, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Yuyang Sun, Chidam Kallingal, Norman Chen
-
Patent number: 8869075Abstract: Approaches for cleaning/resolving lithographic hotspots (e.g., during a simulation phase of semiconductor design) are provided. Typically, a hotspot will be identified in a first polygon (having a first color) of a lithographic pattern or contour. Once a hotspot has been identified, a location (e.g., another portion of the first polygon or in a second polygon of the lithographic pattern having the first color) proximate the hotspot will be identified to place a stitch marker. Once the location has been identified, a stitch marker will be placed at that location. Then, a color of the stitch marked location will be changed to a second color, and the resulting lithographic pattern can be further processed to clean/resolve the hotspot.Type: GrantFiled: December 18, 2012Date of Patent: October 21, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Yuyang Sun, Chidambaram Kallingal, Marc Tarabbia
-
Publication number: 20140253902Abstract: One illustrative method disclosed herein involves identifying an overall target pattern comprised of at least one hole-type feature, decomposing the overall target pattern into at least a first sub-target pattern and a second sub-target pattern, wherein the first sub-target pattern and the second sub-target pattern each comprise at least one common hole-type feature, generating a first set of mask data information corresponding to the first sub-target pattern, and generating a second set of mask data information corresponding to the second sub-target pattern.Type: ApplicationFiled: May 23, 2014Publication date: September 11, 2014Applicant: GLOBALFOUNDRIES Inc.Inventors: Yuyang Sun, Norman S. Chen, Jian Liu
-
Publication number: 20140235055Abstract: Methods are provided for fabricating semiconductor integrated circuits including isolated trench features. In one embodiment, a method includes providing a semiconductor substrate with an overlying process layer. A trench pattern to be etched into the process layer is determined and that trench pattern is decomposed into first and second patterns, the second pattern including an isolated trench. First and second lithographic masks are formed to implement the first and second patterns, the second mask implementing the second pattern, the isolated trench, and a plurality of density balancer patterns symmetrically positioned with respect to the isolated trench. A first resist layer is patterned with the first lithographic mask and the process layer is etched with the first resist layer. A second resist layer is patterned with the second lithographic mask and the process layer is etched with the second resist layer to implement the required trench pattern in the process layer.Type: ApplicationFiled: February 15, 2013Publication date: August 21, 2014Applicant: GLOBALFOUNDRIES, INC.Inventors: Sohan Mehta, Norman Chen, Yuyang Sun, Matthew Herrick, Shyam Pal, Jeong Soo Kim
-
Publication number: 20140223390Abstract: A method includes receiving a design layout file for an integrated circuit device in a computing apparatus. The design layout file specifies dimensions of a plurality of features. The design layout file is decomposed to a plurality of colored layout files, each colored layout file representing a particular reticle in a multiple patterning process. Each of the colored layout files is retargeted separately in the computing apparatus to generate a plurality of retargeted colored layout files. Retargeting each of the colored layout files includes increasing dimensions of a first plurality of features based on spacings between the first plurality of features and adjacent features. The retargeted layout files are combined to generate a combined layout file. Features in the combined layout file are retargeted in the computing apparatus to increase dimensions of a second plurality of features based on spacings between the second plurality of features and adjacent features.Type: ApplicationFiled: February 6, 2013Publication date: August 7, 2014Applicant: GLOBALFOUNDRIES INC.Inventors: Yuyang Sun, Chidam Kallingal, Norman Chen
-
Patent number: 8782571Abstract: One illustrative method disclosed herein involves identifying an overall target pattern comprised of at least one hole-type feature, decomposing the overall target pattern into at least a first sub-target pattern and a second sub-target pattern, wherein the first sub-target pattern and the second sub-target pattern each comprise at least one common hole-type feature, generating a first set of mask data information corresponding to the first sub-target pattern, and generating a second set of mask data information corresponding to the second sub-target pattern.Type: GrantFiled: March 8, 2012Date of Patent: July 15, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Yuyang Sun, Norman S. Chen, Jian Liu
-
Publication number: 20140173533Abstract: Approaches for cleaning/resolving lithographic hotspots (e.g., during a simulation phase of semiconductor design) are provided. Typically, a hotspot will be identified in a first polygon (having a first color) of a lithographic pattern or contour. Once a hotspot has been identified, a location (e.g., another portion of the first polygon or in a second polygon of the lithographic pattern having the first color) proximate the hotspot will be identified to place a stitch marker. Once the location has been identified, a stitch marker will be placed at that location. Then, a color of the stitch marked location will be changed to a second color, and the resulting lithographic pattern can be further processed to clean/resolve the hotspot.Type: ApplicationFiled: December 18, 2012Publication date: June 19, 2014Applicant: GLOBALFOUNDRIES INC.Inventors: Yuyang Sun, Chidambaram Kallingal, Marc Tarabbia
-
Publication number: 20130236836Abstract: One illustrative method disclosed herein involves identifying an overall target pattern comprised of at least one hole-type feature, decomposing the overall target pattern into at least a first sub-target pattern and a second sub-target pattern, wherein the first sub-target pattern and the second sub-target pattern each comprise at least one common hole-type feature, generating a first set of mask data information corresponding to the first sub-target pattern, and generating a second set of mask data information corresponding to the second sub-target pattern.Type: ApplicationFiled: March 8, 2012Publication date: September 12, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Yuyang Sun, Norman S. Chen, Jian Liu