Patents by Inventor Yu-yeong Jo

Yu-yeong Jo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230378335
    Abstract: The present disclosure provides a semiconductor device with a multi-bridge channel field effect transistor. In some embodiments, a semiconductor device includes a substrate, an active pattern that extends in a first horizontal direction on the substrate, a first nanosheet, a second nanosheet, and a gate electrode. The first nanosheet is spaced apart from the active pattern in a vertical direction, and includes a first layer, a second layer disposed on and in contact with the first layer, and a third layer disposed on and in contact with the second layer. The first and third layers include a first material, and the second layer includes a different second material. The second nanosheet is disposed on the first nanosheet and spaced apart from the first nanosheet in the vertical direction. The gate electrode extends in a second horizontal direction on the active pattern and surrounds the first and second nanosheets.
    Type: Application
    Filed: December 7, 2022
    Publication date: November 23, 2023
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Keun LIM, Hyo Hoon BYEON, Do Hyun GO, Un Ki KIM, Yu Yeong JO, Jin Yeong CHO
  • Patent number: 10790361
    Abstract: Provided is a semiconductor device including: a fin structure on a substrate including a negative channel field-effect transistor (nFET) region and a positive channel field-effect transistor (pFET) region; a gate structure on the fin structure; and a source/drain structure adjacent to the gate structure, wherein the source/drain structure formed in the nFET region is an epitaxial layer including an n-type impurity at a concentration of about 1.8×1021/cm3 or more, includes silicon (Si) and germanium (Ge) on an outer portion of the source/drain structure, and includes Si but not Ge in an inner portion of the source/drain structure, wherein an inclined surface contacting an uppermost surface of the source/drain structure forms an angle of less than about 54.7° with a top surface of the fin structure.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: September 29, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-woo Kim, Hyun-ho Noh, Yong-seung Kim, Dong-suk Shin, Kwan-heum Lee, Yu-yeong Jo
  • Publication number: 20190259840
    Abstract: Provided is a semiconductor device including: a fin structure on a substrate including a negative channel field-effect transistor (nFET) region and a positive channel field-effect transistor (pFET) region; a gate structure on the fin structure; and a source/drain structure adjacent to the gate structure, wherein the source/drain structure formed in the nFET region is an epitaxial layer including an n-type impurity at a concentration of about 1.8×1021/cm3 or more, includes silicon (Si) and germanium (Ge) on an outer portion of the source/drain structure, and includes Si but not Ge in an inner portion of the source/drain structure, wherein an inclined surface contacting an uppermost surface of the source/drain structure forms an angle of less than about 54.7° with a top surface of the fin structure.
    Type: Application
    Filed: April 23, 2019
    Publication date: August 22, 2019
    Inventors: Dong-woo Kim, Hyun-ho Noh, Yong-seung Kim, Dong-suk Shin, Kwan-heum Lee, Yu-yeong Jo
  • Patent number: 10304932
    Abstract: Provided is a semiconductor device including: a fin structure on a substrate including a negative channel field-effect transistor (nFET) region and a positive channel field-effect transistor (pFET) region; a gate structure on the fin structure; and a source/drain structure adjacent to the gate structure, wherein the source/drain structure formed in the nFET region is an epitaxial layer including an n-type impurity at a concentration of about 1.8×1021/cm3 or more, includes silicon (Si) and germanium (Ge) on an outer portion of the source/drain structure, and includes Si but not Ge in an inner portion of the source/drain structure, wherein an inclined surface contacting an uppermost surface of the source/drain structure forms an angle of less than about 54.7° with a top surface of the fin structure.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: May 28, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-woo Kim, Hyun-ho Noh, Yong-seung Kim, Dong-suk Shin, Kwan-heum Lee, Yu-yeong Jo
  • Publication number: 20190006469
    Abstract: Provided is a semiconductor device including: a fin structure on a substrate including a negative channel field-effect transistor (nFET) region and a positive channel field-effect transistor (pFET) region; a gate structure on the fin structure; and a source/drain structure adjacent to the gate structure, wherein the source/drain structure formed in the nFET region is an epitaxial layer including an n-type impurity at a concentration of about 1.8×1021/cm3 or more, includes silicon (Si) and germanium (Ge) on an outer portion of the source/drain structure, and includes Si but not Ge in an inner portion of the source/drain structure, wherein an inclined surface contacting an uppermost surface of the source/drain structure forms an angle of less than about 54.7° with a top surface of the fin structure.
    Type: Application
    Filed: January 15, 2018
    Publication date: January 3, 2019
    Inventors: Dong-woo Kim, Hyun-ho Noh, Yong-seung Kim, Dong-suk Shin, Kwan-heum Lee, Yu-yeong Jo