Patents by Inventor Yuying Wei

Yuying Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11776821
    Abstract: A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die. An encapsulant is over the protrusion of the substrate, the encapsulant extending beneath the first die, and the encapsulant extending beneath the second die.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: October 3, 2023
    Assignee: Intel Corporation
    Inventors: Ziyin Lin, Vipul Mehta, Edvin Cetegen, Yuying Wei, Sushrutha Gujjula, Nisha Ananthakrishnan, Shan Zhong
  • Publication number: 20220165585
    Abstract: A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die.
    Type: Application
    Filed: February 10, 2022
    Publication date: May 26, 2022
    Inventors: Ziyin LIN, Vipul MEHTA, Edvin CETEGEN, Yuying WEI, Sushrutha GUJJULA, Nisha ANANTHAKRISHNAN, Shan ZHONG
  • Patent number: 11282717
    Abstract: A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die. The substrate protrusion can enable void-free underfill.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: March 22, 2022
    Assignee: Intel Corporation
    Inventors: Ziyin Lin, Vipul Mehta, Edvin Cetegen, Yuying Wei, Sushrutha Gujjula, Nisha Ananthakrishnan, Shan Zhong
  • Publication number: 20200006169
    Abstract: A structure including a barrier is described. In embodiments, a micro-electronic component may have a first face and a second face, wherein the second face includes interconnect structures and is opposite the first face. A fill material, such as a capillary underfill material (CUF), may fill a gap between the micro-electronic component and the substrate and substantially surround the interconnect structures. In embodiments, a barrier structure may be located on the surface of the substrate and along a perimeter or outside perimeter of the micro-electronic component, wherein a height of the barrier structure exceeds a height of the fill material in at least a portion of an open region of the substrate to confine the fill material to an area bordered by the barrier structure.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Inventors: William WARREN, Taylor GAINES, Frederick ATADANA, Edvin CETEGEN, Vipul MEHTA, Hsin-Yu LI, Yuying WEI, Yang GUO, Ren ZHANG
  • Publication number: 20190304808
    Abstract: A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 3, 2019
    Inventors: Ziyin LIN, Vipul MEHTA, Edvin CETEGEN, Yuying WEI, Sushrutha GUJJULA, Nisha ANANTHAKRISHNAN, Shan ZHONG
  • Patent number: 10115606
    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include modifying an underfill material with one of a thiol adhesion promoter, an azole coupling agent, surface modified filler, and peroxide based cross-linking polymer chemistries to greatly enhance adhesion in package structures utilizing the embodiments herein.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: October 30, 2018
    Assignee: Intel Corporation
    Inventors: Yiqun Bai, Yuying Wei, Arjun Krishnan, Suriyakala Ramalingam, Yonghao Xiu, Beverly J. Canham, Sivakumar Nagarajan, Saikumar Jayaraman, Nisha Ananthakrishnan
  • Publication number: 20170053858
    Abstract: Embodiments herein may relate to a patch on interposer (PoINT) architecture. In embodiments, the PoINT architecture may include a plurality of solder joints between a patch and an interposer. The solder joints may include a relatively high temperature solder ball and a relatively low temperature solder paste that at least partially surrounds the solder ball. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: August 20, 2015
    Publication date: February 23, 2017
    Inventors: Jan Krajniak, Carl L. Deppisch, Kabirkumar J. Mirpuri, Hongjin Jiang, Fay Hua, Yuying Wei, Beverly J. Canham, Jiongxin Lu, Mukul P. Renavikar
  • Publication number: 20160240395
    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include modifying an underfill material with one of a thiol adhesion promoter, an azole coupling agent, surface modified filler, and peroxide based cross-linking polymer chemistries to greatly enhance adhesion in package structures utilizing the embodiments herein.
    Type: Application
    Filed: April 26, 2016
    Publication date: August 18, 2016
    Inventors: Yiqun Bai, Yuying Wei, Arjun Krishnan, Suriyakala Ramalingam, Yonghao Xiu, Beverly J. Canham, Sivakumar Nagarajan, Saikumar Jayaraman, Nisha Ananthakrishnan
  • Patent number: 9330993
    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include modifying an underfill material with one of a thiol adhesion promoter, an azole coupling agent, surface modified filler, and peroxide based cross-linking polymer chemistries to greatly enhance adhesion in package structures utilizing the embodiments herein.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: May 3, 2016
    Assignee: Intel Corporation
    Inventors: Yiqun Bai, Yuying Wei, Arjun Krishnan, Suriyakala Ramalingam, Yonghao Xiu, Beverly J. Canham, Sivakumar Nagarajan, Saikumar Jayaraman, Nisha Ananthakrishnan
  • Publication number: 20140175634
    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include modifying an underfill material with one of a thiol adhesion promoter, an azole coupling agent, surface modified filler, and peroxide based cross-linking polymer chemistries to greatly enhance adhesion in package structures utilizing the embodiments herein.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 26, 2014
    Inventors: Yiqun Bai, Yuying Wei, Arjun Krishnan, Suriyakala Ramalingam, Yonghao Xiu, Beverly J. Canham, Sivakumar Nagarajan, Saikumar Jayaraman, Nisha Ananthakrishnan