Abstract: An electronic package is provided in which an electronic module and a heat dissipation structure combined with the electronic module are disposed on a carrier structure, and at least one adjustment structure is coupled with the heat dissipation structure and located around the electronic module. Therefore, the adjustment structure disperses thermal stress to avoid warpage of the electronic module.

Abstract: A polymer plastic front plate comprises: a plastic substrate and a hard coating layer formed on an adhesion surface of the plastic substrate. The hard coating layer comprises: organic-inorganic hybrid UV oligomer, high Tg UV resin additive, a plurality of dispersed flaky nano inorganic material, and photo initiator, so as to form a gas barrier hard coating layer with high surface dyne value (>44 dyne) on the adhesion surface of the plastic substrate. It not only has good ink printability and OCA adhesiveness, but also inhibits the diffusion of fugitive gas from polymer plastic front plates during high-temperature, high-temperature and high-humidity, high-low temperature thermal shocks and other harsh automotive industry environmental tests. The gas can be avoided from entering the OCA layer, thereby solving the problems of bubbles and delamination after the environmental tests are performed.

Abstract: Embodiments of the present disclosure provide a radio frequency (RF) return device. One example RF return device generally includes a bracket for coupling to a chamber body, a cover coupled to the bracket, and a contact plate coupled to the cover and configured contact a substrate support. Using the RF return device described herein generally enables a reduction in temperature that the RF return device and its various components are exposed to, increasing the durability and lifetime of the RF return device. In addition, the RF return device disclosed herein may block chemicals (e.g., fluorine (F)) used in the process chamber from attacking components included in the RF return device, thereby providing enhanced protection to the RF return device.

Abstract: The present invention provides a PTX3 monoclonal antibody or antibody Fab fragment thereof and use thereof. The aforementioned monoclonal antibody or antibody Fab fragment thereof specifically inhibit or slow down the binding of PTX3 to the PTX3 receptor, and may be used for a kit and method for detecting PTX3, and a pharmaceutical composition which inhibits or slows down diseases or symptoms associated with PTX3 and PTX3 receptor binding, and a use thereof.

Abstract: A semiconductor structure includes a semiconductor substrate, an interconnection structure, a color filter, and a first isolation structure. The semiconductor substrate includes a first surface and a second surface opposite to the first surface. The interconnection structure is disposed over the first surface, and the color filter is disposed over the second surface. The first isolation structure includes a bottom portion, an upper portion and a diffusion barrier layer surrounding a sidewall of the upper portion. A top surface of the upper portion of the first isolation structure extends into and is in contact with a dielectric layer of the interconnection structure.

Abstract: An intelligent construction robot system having a learning module that performs machine learning based on point cloud data and building information data during a machine learning phase to generate a building model and store it; and a judging module that evaluates the similarity between the point cloud data and each of the building models during a machine interpretation phase to determine whether to use the building model with the highest similarity or to generate another building model, and the judging module generates a construction schedule corresponding to the building model.

Abstract: A method includes depositing a slurry onto a polishing pad of a chemical mechanical polishing (CMP) station. A workpiece is polished and polishing by-products and slurry are removed from the polishing pad by a vacuum head. A CMP apparatus includes a polishing pad configured to rotate during a CMP process. The apparatus also includes a slurry dispenser configured to deposit a slurry onto a polishing surface of the polishing pad. The apparatus further includes a momentum vacuum assembly including a slotted opening facing the polishing surface of the polishing pad. The apparatus also includes a first suction line coupled to an upper portion of the momentum vacuum assembly and leading to a first vacuum source, the first suction line configured to transport polishing products which have been removed from the polishing pad through the slotted opening.

Abstract: A semiconductor structure includes a metal gate structure including a gate dielectric layer and a gate electrode, a conductive layer disposed on the gate electrode, and a gate contact disposed on the conductive layer. The conductive layer extends from a position below a top surface of the metal gate structure to a position above the top surface of the metal gate structure. The gate electrode includes at least a first metal, and the conductive layer includes at least the first metal and a second metal different from the first metal. Laterally the conductive layer is fully between opposing sidewalls of the metal gate structure.

Abstract: A method of forming a semiconductor device includes forming a first epitaxial layer over a substrate to form a wafer, depositing a dielectric layer over the first epitaxial layer, patterning the dielectric layer to form an opening, etching the first epitaxial layer through the opening to form a recess, forming a second epitaxial layer in the recess, etching the dielectric layer to expose a top surface of the first epitaxial layer, and planarizing the exposed top surface of the first epitaxial layer and a top surface of the second epitaxial layer.

Abstract: A method includes following steps. A single-crystalline two-dimensional (2D) semiconductor layer is formed over a substrate. A single-crystalline 2D material layer is epitaxially grown on the single-crystalline 2D semiconductor layer. The single-crystalline 2D material layer is lattice-matched with the single-crystalline 2D semiconductor layer. A semiconductor device is over the single-crystalline 2D semiconductor layer.

Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.

Abstract: A method of forming a semiconductor device includes forming a first epitaxial layer over a substrate to form a wafer, depositing a dielectric layer over the first epitaxial layer, patterning the dielectric layer to form an opening, etching the first epitaxial layer through the opening to form a recess, forming a second epitaxial layer in the recess, etching the dielectric layer to expose a top surface of the first epitaxial layer, and planarizing the exposed top surface of the first epitaxial layer and a top surface of the second epitaxial layer.

Abstract: The present disclosure generally provides an apparatus and method for gas diffuser support structure for a vacuum chamber. The gas diffuser support structure comprises a backing plate having a central bore, and a gas deflector having a length and a width unequal to the length coupled to the backing plate by a plurality of outward fasteners coupled to a plurality of outward threaded holes formed in the backing plate, in which a spacer is disposed between the backing plate and the gas deflector, and in which a length to width ratio of the gas deflector is about 0.1:1 to about 10:1.

Abstract: An epitaxial structure includes a substrate and a dielectric layer. The dielectric layer is on the substrate. The substrate comprises a single crystal metal or a single crystal 2D material. The dielectric layer is in physical contact with the substrate. The dielectric layer comprises a non-perovskite structure with defined grain orientation with ferroelectric (FE) phase or antiferroelectric (AFE) phase.

Abstract: A polymer plastic front plate comprises: a plastic substrate and a hard coating layer formed on an adhesion surface of the plastic substrate. The hard coating layer comprises: organic-inorganic hybrid UV oligomer, high Tg UV resin additive, a plurality of dispersed flaky nano inorganic material, and photo initiator, so as to form a gas barrier hard coating layer with high surface dyne value (>44 dyne) on the adhesion surface of the plastic substrate. It not only has good ink printability and OCA adhesiveness, but also inhibits the diffusion of fugitive gas from polymer plastic front plates during high-temperature, high-temperature and high-humidity, high-low temperature thermal shocks and other harsh automotive industry environmental tests. The gas can be avoided from entering the OCA layer, thereby solving the problems of bubbles and delamination after the environmental tests are performed.

Abstract: A chip package structure includes a substrate, a chip, a light-permeable element, and an adhesive element. The chip is disposed on the substrate. The light-permeable element is disposed above the chip. The adhesive element is connected between the chip and the light-permeable element. The adhesive element surrounds the chip for formation of an accommodating space, and the chip is located in the accommodating space. The adhesive element includes two material layers having complementary visible light absorption spectra, such that the adhesive element is capable of being used to absorb full visible spectrum light.

Abstract: A wafer pod transfer assembly includes a wafer pod port to receive a wafer pod, a transfer axle coupled to the wafer pod port, a shaft receiver, a shaft coupled to the transfer axle and to the shaft receiver, a pin through the shaft receiver and through the shaft, wherein the pin comprises a first end and a second end, opposite the first end, and a pin buckle including a first loop and a second loop. The pin buckle is coupled to the pin, the first loop encircles the first end of the pin, and the second loop encircles the second end of the pin.

Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.

Abstract: An image recognition method includes the steps of: receiving a captured image; acquiring a focusing zone image from a portion of the captured image; processing the captured image and/or the focusing zone image and then making the two images into a batch of image information; and executing an image analysis procedure on the batch of image information to generate an analysis result.

Abstract: An image processing circuit performs super-resolution (SR) operations. The image processing circuit includes memory to store multiple parameter sets of multiple artificial intelligence (AI) models. The image processing circuit further includes an image guidance module, a parameter decision module, and an SR engine. The image guidance module operates to detect a representative feature in an image sequence including a current frame and past frames within a time window. The parameter decision module operates to adjust parameters of one or more AI models based on a measurement of the representative feature. The SR engine operates to process the current frame using the one or more AI models with the adjusted parameters to thereby generate a high-resolution image for display.