Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer adjacent to the gate structure, wherein the first spacer comprises silicon carbon nitride (SiCN); forming a second spacer adjacent to the first spacer, wherein the second spacer comprises silicon oxycarbonitride (SiOCN); and forming a source/drain region adjacent to two sides of the second spacer.

Abstract: A method of forming a semiconductor device includes: forming a semiconductor structure having source/drain regions, a fin disposed between the source/drain regions, and a dummy gate disposed on the fin and surrounded by a spacer; removing the dummy gate to form a gate trench which is defined by a trench-defining wall; forming a gate dielectric layer on the trench-defining wall; forming a work function structure on the gate dielectric layer; forming a resist layer to fill the gate trench; removing a top portion of the resist layer; removing the work function structure exposed from the resist layer using a wet chemical etchant; removing the resist layer; and forming a conductive gate in the gate trench.

Abstract: A semiconductor structure has a frontside and a backside. The semiconductor structure includes an isolation structure at the backside; one or more transistors at the frontside, wherein the one or more transistors have source/drain epitaxial features; two metal plugs through the isolation structure and contacting two of the source/drain electrodes from the backside; and a dielectric liner filling a space between the two metal plugs, wherein the dielectric liner partially or fully surrounds an air gap between the two metal plugs.

Abstract: A method for processing a curved plastic panel is to first form a hard coating layer, an optical function layer, and a printing layer on a flat plastic substrate, and then cut it into a predetermined shape, and then use a hot pressing and curving device to perform a hot pressing and curving process to the flat plastic substrate in order to make it becoming a curved plastic substrate. The hot pressing and curving device can simultaneously perform hot pressing during the heating process, and has the functions of real-time monitoring of the local temperature and the local curvature forming state, and then feedback to the local heating and curvature forming mechanism for adjustments. The monitoring of temperature and curvature can be divided into multiple stages, which can be monitored stage by stage and adjusted for heating or curvature forming to improve production yield.

Abstract: A semiconductor structure includes a source/drain feature in the semiconductor layer. The semiconductor structure includes a dielectric layer over the source/drain feature. The semiconductor structure includes a silicide layer over the source/drain feature. The semiconductor structure includes a barrier layer over the silicide layer. The semiconductor structure includes a seed layer over the barrier layer. The semiconductor structure includes a metal layer between a sidewall of the seed layer and a sidewall of the dielectric layer, a sidewall of each of the silicide layer, the barrier layer, and the metal layer directly contacting the sidewall of the dielectric layer. The semiconductor structure includes a source/drain contact over the seed layer.

Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a semiconductor substrate having sidewalls that form one or more trenches. The one or more trenches are disposed along opposing sides of a photodiode and vertically extend from an upper surface of the semiconductor substrate to within the semiconductor substrate. A doped region is arranged along the upper surface of the semiconductor substrate and along opposing sides of the photodiode. A first dielectric lines the sidewalls of the semiconductor substrate and the upper surface of the semiconductor substrate. A second dielectric lines sidewalls and an upper surface of the first dielectric. The doped region has a width laterally between a side of the photodiode and a side of the first dielectric. The width of the doped region varies at different heights along the side of the photodiode.

Abstract: A method for synthesizing the all-silica zeolite beta with small crystal size is disclosed. This method comprises the steps of: (a) forming a reaction mixture comprising (1) a source of silicon dioxide (SiO2), (2) a source of fluoride ions (F?), (3) a source of tetraethylammonium cations (TEA+), and (4) water (H2O), at predetermined mole ratios of the source of silicon dioxide, the source of fluoride ions, the source of tetraethylammonium cations, and water; (b) crystallizing the reaction mixture; and (c) recovering the crystalline material formed, wherein the pH of the mixture before crystallization has a value of 6 to 9, and the pH of the mixture after crystallization has a value of 6 to 8. This improved method gives a fast and efficient way of synthesis of all-silica zeolite beta with an average crystal size of less than 5 ?m.

Abstract: A method for synthesizing the all-silica zeolite beta with small crystal size is disclosed. This method comprises the steps of: (a) forming a reaction mixture comprising (1) a source of silicon dioxide (SiO2), (2) a source of fluoride ions (F?), (3) a source of tetraethylammonium cations (TEA+), and (4) water (H2O), at predetermined mole ratios of the source of silicon dioxide, the source of fluoride ions, the source of tetraethylammonium cations, and water; (b) crystallizing the reaction mixture; and (c) recovering the crystalline material formed, wherein the pH of the mixture before crystallization has a value of 6 to 9, and the pH of the mixture after crystallization has a value of 6 to 8. This improved method gives a fast and efficient way of synthesis of all-silica zeolite beta with an average crystal size of less than 5 ?m.