Patents by Inventor Yuzo Hamanaka
Yuzo Hamanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7556985Abstract: A semiconductor device has a resin package layer on a principal surface of a semiconductor chip, on which a number of bump electrodes are formed, wherein the semiconductor device has a chamfer surface or a stepped surface on a top edge part such that the external shock or stress applied to such an edge part is dissipated by the chamfer surface of the stepped surface.Type: GrantFiled: October 14, 2005Date of Patent: July 7, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Norio Fukasawa, Hirohisa Matsuki, Kenichi Nagashige, Yuzo Hamanaka, Muneharu Morioka
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Patent number: 7064047Abstract: A semiconductor device has a resin package layer on a principal surface of a semiconductor chip, on which a number of bump electrodes are formed, wherein the semiconductor device has a chamfer surface or a stepped surface on a top edge part such that the external shock or stress applied to such an edge part is dissipated by the chamfer surface of the stepped surface.Type: GrantFiled: July 19, 2004Date of Patent: June 20, 2006Assignee: Fujitsu LimitedInventors: Norio Fukasawa, Hirohisa Matsuki, Kenichi Nagashige, Yuzo Hamanaka, Muneharu Morioka
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Publication number: 20060030127Abstract: A semiconductor device has a resin package layer on a principal surface of a semiconductor chip, on which a number of bump electrodes are formed, wherein the semiconductor device has a chamfer surface or a stepped surface on a top edge part such that the external shock or stress applied to such an edge part is dissipated by the chamfer surface of the stepped surface.Type: ApplicationFiled: October 14, 2005Publication date: February 9, 2006Applicant: FUJITSU LIMITEDInventors: Norio Fukasawa, Hirohisa Matsuki, Kenichi Nagashige, Yuzo Hamanaka, Muneharu Morioka
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Patent number: 6987054Abstract: A semiconductor device has a resin package layer on a principal surface of a semiconductor chip, on which a number of bump electrodes are formed, wherein the semiconductor device has a chamfer surface or a stepped surface on a top edge part such that the external shock or stress applied to such an edge part is dissipated by the chamfer surface of the stepped surface.Type: GrantFiled: March 15, 2002Date of Patent: January 17, 2006Assignee: Fujitsu LimitedInventors: Norio Fukasawa, Hirohisa Matsuki, Kenichi Nagashige, Yuzo Hamanaka, Muneharu Morioka
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Publication number: 20040259346Abstract: A semiconductor device has a resin package layer on a principal surface of a semiconductor chip, on which a number of bump electrodes are formed, wherein the semiconductor device has a chamfer surface or a stepped surface on a top edge part such that the external shock or stress applied to such an edge part is dissipated by the chamfer surface of the stepped surface.Type: ApplicationFiled: July 19, 2004Publication date: December 23, 2004Applicant: FUJITSU LIMITEDInventors: Norio Fukasawa, Hirohisa Matsuki, Kenichi Nagashige, Yuzo Hamanaka, Muneharu Morioka
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Patent number: 6784542Abstract: A semiconductor device has a resin package layer on a principal surface of a semiconductor chip, on which a number of bump electrodes are formed, wherein the semiconductor device has a chamfer surface or a stepped surface on a top edge part such that the external shock or stress applied to such an edge part is dissipated by the chamfer surface of the stepped surface.Type: GrantFiled: July 15, 2003Date of Patent: August 31, 2004Assignee: Fujitsu LimitedInventors: Norio Fukasawa, Hirohisa Matsuki, Kenichi Nagashige, Yuzo Hamanaka, Muneharu Morioka
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Publication number: 20040012088Abstract: A semiconductor device has a resin package layer on a principal surface of a semiconductor chip, on which a number of bump electrodes are formed, wherein the semiconductor device has a chamfer surface or a stepped surface on a top edge part such that the external shock or stress applied to such an edge part is dissipated by the chamfer surface of the stepped surface.Type: ApplicationFiled: July 15, 2003Publication date: January 22, 2004Applicant: FUJITSU LIMITED,Inventors: Norio Fukasawa, Hirohisa Matsuki, Kenichi Nagashige, Yuzo Hamanaka, Muneharu Morioka
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Patent number: 6657282Abstract: A semiconductor device has a resin package layer on a principal surface of a semiconductor chip, on which a number of bump electrodes are formed, wherein the semiconductor device has a chamfer surface or a stepped surface on a top edge part such that the external shock or stress applied to such an edge part is dissipated by the chamfer surface of the stepped surface.Type: GrantFiled: March 15, 2002Date of Patent: December 2, 2003Assignee: Fujitsu LimitedInventors: Norio Fukasawa, Hirohisa Matsuki, Kenichi Nagashige, Yuzo Hamanaka, Muneharu Morioka
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Patent number: 6511620Abstract: A method of producing semiconductor devices which have an excellent separability from a metal mold after resin encapsulation and thus eliminates the need to clean the metal mold. A metal mold for producing such semiconductor devices is also provided. According to the method of the present invention, the metal mold is first opened, and two separation sheets are disposed on dividing surfaces including cavity forming surfaces of a first metal mold and a second metal mold. A substrate is then placed on one of the separation sheets, with its semiconductor chip formed surface facing the second metal mold. An encapsulation resin is provided on the substrate placed on one of the separation sheets. The metal mold in a heated state is closed and pressed to form a resin layer for encapsulating electrodes formed on the substrate. The metal mold is again opened, and the resin-encapsulated substrate is taken out of the metal mold.Type: GrantFiled: February 23, 2000Date of Patent: January 28, 2003Assignees: Fujitsu Limited, Fujitsu Automation LimitedInventors: Toshimi Kawahara, Hirohisa Matsuki, Yasuhiro Shinma, Yoshiyuki Yoneda, Norio Fukasawa, Yuzo Hamanaka, Kenichi Nagashige, Takashi Hozumi
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Patent number: 6471501Abstract: A mold for press-molding a resin package body includes a lower mold and an upper mold, wherein the upper mold includes a press plate held in a tiltable manner with respect to a press head used for urging the upper mold against the lower mold and a lock mechanism for locking the press plate. The lower mold includes an inner die carrying a semiconductor device and a resin tablet and an outer die surrounding the inner die in a manner movable up and down with respect to the inner die. In operation, the press plate is first engaged with the outer die in the unlocked state to achieve an exact parallelism with respect to the inner die, and after locking the press plate and melting the resin tablet, the press plate is urged further toward the inner die while simultaneously lowering the outer die such that the space formed by the lower die, outer die and the press plate for accommodating a semiconductor chip is collapsed.Type: GrantFiled: March 18, 1999Date of Patent: October 29, 2002Assignee: Fujitsu LimitedInventors: Yasuhiro Shinma, Muneharu Morioka, Norio Fukasawa, Yuzo Hamanaka, Tadashi Uno, Hirohisa Matsuki, Kenichi Nagashige
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Patent number: 6469370Abstract: In a semiconductor device of the present invention and a production method thereof, an electronic circuit is provided in a semiconductor substrate, the electronic circuit having terminals. An internal wiring pattern is provided in the substrate, the internal wiring pattern being connected to the electronic circuit terminals. A protective layer is provided on the substrate, the protective layer covering the substrate. Vias are provided on the substrate so as to project from the protective layer, the vias being connected to the internal wiring pattern at arbitrary positions on the substrate. An external wiring pattern is provided on the protective layer, the external wiring pattern being connected to the vias. Projection electrodes are connected to the external wiring pattern, the projection electrodes having a predetermined height above the external wiring pattern.Type: GrantFiled: February 1, 2000Date of Patent: October 22, 2002Assignee: Fujitsu LimitedInventors: Toshimi Kawahara, Hirohisa Matsuki, Yasuhiro Shinma, Yoshiyuki Yoneda, Norio Fukasawa, Yuzo Hamanaka, Kenichi Nagashige, Takashi Hozumi
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Patent number: 6455920Abstract: A semiconductor device has a resin package layer on a principal surface of a semiconductor chip, on which a number of bump electrodes are formed, wherein the semiconductor device has a chamfer surface or a stepped surface on a top edge part such that the external shock or stress applied to such an edge part is dissipated by the chamfer surface of the stepped surface.Type: GrantFiled: September 25, 1998Date of Patent: September 24, 2002Assignee: Fujitsu LimitedInventors: Norio Fukasawa, Hirohisa Matsuki, Kenichi Nagashige, Yuzo Hamanaka, Muneharu Morioka
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Publication number: 20020089040Abstract: A semiconductor device has a resin package layer on a principal surface of a semiconductor chip, on which a number of bump electrodes are formed, wherein the semiconductor device has a chamfer surface or a stepped surface on a top edge part such that the external shock or stress applied to such an edge part is dissipated by the chamfer surface of the stepped surface.Type: ApplicationFiled: March 15, 2002Publication date: July 11, 2002Applicant: FIJITSU LIMITEDInventors: Norio Fukasawa, Hirohisa Matsuki, Kenichi Nagashige, Yuzo Hamanaka, Muneharu Morioka
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Publication number: 20020089054Abstract: A semiconductor device has a resin package layer on a principal surface of a semiconductor chip, on which a number of bump electrodes are formed, wherein the semiconductor device has a chamfer surface or a stepped surface on a top edge part such that the external shock or stress applied to such an edge part is dissipated by the chamfer surface of the stepped surface.Type: ApplicationFiled: March 15, 2002Publication date: July 11, 2002Applicant: FUJITSU LIMITEDInventors: Norio Fukasawa, Hirohisa Matsuki, Kenichi Nagashige, Yuzo Hamanaka, Muneharu Morioka
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Publication number: 20010011772Abstract: A semiconductor device has a resin package layer on a principal surface of a semiconductor chip, on which a number of bump electrodes are formed, wherein the semiconductor device has a chamfer surface or a stepped surface on a top edge part such that the external shock or stress applied to such an edge part is dissipated by the chamfer surface of the stepped surface.Type: ApplicationFiled: September 25, 1998Publication date: August 9, 2001Applicant: FUJITSU LIMITEDInventors: NORIO FUKASAWA, HIROHISA MATSUKI, KENICHI NAGASHIGE, YUZO HAMANAKA, MUNEHARU MORIOKA