Patents by Inventor Yuzo Neishi

Yuzo Neishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7573140
    Abstract: A semiconductor device includes: a semiconductor substrate that has an integrated circuit; a plurality of electrodes that is formed on the semiconductor substrate, the plurality of the electrodes being electrically coupled to the integrated circuit; a passivation film that is formed on the semiconductor substrate, the passivation film having an opening on at least a part of one of the plurality of electrodes; a resin protrusion that is disposed on the passivation film; and a plurality of wiring lines that extend to a surface of the resin protrusion, each of the plurality of wiring lines extending from one of the plurality of the electrodes, a first portion of each of the plurality of wiring lines being positioned at an uppermost edge of the resin protrusion, a second portion of each of the plurality of wiring lines being positioned between one of the plurality of electrodes and the uppermost edge of the resin protrusion, a width of the first portion of each of the plurality of wiring lines being narrower than
    Type: Grant
    Filed: July 28, 2008
    Date of Patent: August 11, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Yuzo Neishi
  • Publication number: 20090051042
    Abstract: A semiconductor device includes: a semiconductor substrate that has an integrated circuit; a plurality of electrodes that is formed on the semiconductor substrate, the plurality of the electrodes being electrically coupled to the integrated circuit; a passivation film that is formed on the semiconductor substrate, the passivation film having an opening on at least a part of one of the plurality of electrodes; a resin protrusion that is disposed on the passivation film; and a plurality of wiring lines that extend to a surface of the resin protrusion, each of the plurality of wiring lines extending from one of the plurality of the electrodes, a first portion of each of the plurality of wiring lines being positioned at an uppermost edge of the resin protrusion, a second portion of each of the plurality of wiring lines being positioned between one of the plurality of electrodes and the uppermost edge of the resin protrusion, a width of the first portion of each of the plurality of wiring lines being narrower than
    Type: Application
    Filed: July 28, 2008
    Publication date: February 26, 2009
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Yuzo NEISHI
  • Publication number: 20080224331
    Abstract: An electronic device includes: a semiconductor chip that includes an integrated circuit, a plurality of electrodes electrically connected to the integrated circuit, and a passivation film formed in a manner that at least a portion of each of the plurality of electrodes is exposed; a resin layer that is formed on the passivation film; a plurality of wirings, each of the plurality of wirings extending from a top surface of each of the plurality of electrodes to a top surface of the resin layer and electrically connected to each of the plurality of electrodes, respectively; a wiring substrate that has a wiring pattern opposing to and electrically connected to portions of the plurality of wirings above the resin layer; and a hardened adhesive resin that is placed between the semiconductor chip and the wiring substrate, wherein the adhesive resin internally has a residual stress that is generated by contraction at the time of hardening the adhesive resin, and a portion of the adhesive resin is disposed between a p
    Type: Application
    Filed: March 12, 2008
    Publication date: September 18, 2008
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Yuzo NEISHI