Abstract: The invention provides an LDMOS transistor of which the time-dependent degrading of the performance due to the trapping of hot electrons in the gate insulation film is decreased. A body layer is disposed in a surface portion of an N? type semiconductor layer. A source layer including an N? type layer is disposed in a surface portion of the body layer. An N? type drift layer is formed in a surface portion of the N? type semiconductor layer. This drift layer includes a first region having a first N type impurity concentration peak region and a second region having a second N type impurity concentration peak region that is positioned deeper than the first N type impurity concentration peak region, the second region adjoining this first region. An N+ type drain layer is formed in a surface portion of the second region.

Abstract: The invention provides an LDMOS transistor of which the time-dependent degrading of the performance due to the trapping of hot electrons in the gate insulation film is decreased. A body layer is disposed in a surface portion of an N?-type semiconductor layer. A source layer including an N?-type layer is disposed in a surface portion of the body layer. An N? type drift layer is formed in a surface portion of the N?-type semiconductor layer. This drift layer includes a first region having a first N type impurity concentration peak region and a second region having a second N type impurity concentration peak region that is positioned deeper than the first N type impurity concentration peak region, the second region adjoining this first region. An N+ type drain layer is formed in a surface portion of the second region.

Abstract: The invention provides an LDMOS transistor of which the time-dependent degrading of the performance due to the trapping of hot electrons in the gate insulation film is decreased. A body layer is disposed in a surface portion of an N?? type semiconductor layer. A source layer including an N? type layer is disposed in a surface portion of the body layer. An N? type drift layer is formed in a surface portion of the N?? type semiconductor layer. This drift layer includes a first region having a first N type impurity concentration peak region and a second region having a second N type impurity concentration peak region that is positioned deeper than the first N type impurity concentration peak region, the second region adjoining this first region. An N+ type drain layer is formed in a surface portion of the second region.

Abstract: A semiconductor device equally turns on the parasitic bipolar transistors in the finger portions of the finger form source and drain electrodes when a surge voltage is applied, even with the P+ type contact layer surrounding the N+ type source layers and the N+ type drain layers connected to the finger form source and drain electrodes. A P+ type contact layer surrounds N+ type source layers and N+ type drain layers. Metal silicide layers are formed on the N+ type source layers, the N+ type drain layers, and a portion of the P+ type contact layer. Finger form source electrodes, finger form drain electrodes, and a P+ type contact electrode surrounding these finger form electrodes are formed, being connected to the metal silicide layers respectively through contact holes formed in an interlayer insulation film deposited on the metal silicide layers.

Abstract: A semiconductor device equally turns on the parasitic bipolar transistors in the finger portions of the finger form source and drain electrodes when a surge voltage is applied, even with the P+ type contact layer surrounding the N+ type source layers and the N+ type drain layers connected to the finger form source and drain electrodes. A P+ type contact layer surrounds N+ type source layers and N+ type drain layers. Metal silicide layers are formed on the N+ type source layers, the N+ type drain layers, and a portion of the P+ type contact layer. Finger form source electrodes, finger form drain electrodes, and a P+ type contact electrode surrounding these finger form electrodes are formed, being connected to the metal silicide layers respectively through contact holes formed in an interlayer insulation film deposited on the metal silicide layers.

Abstract: The invention provides an LDMOS transistor of which the time-dependent degrading of the performance due to the trapping of hot electrons in the gate insulation film is decreased. A body layer is disposed in a surface portion of an N? type semiconductor layer. A source layer including an N? type layer is disposed in a surface portion of the body layer. An N? type drift layer is formed in a surface portion of the N? type semiconductor layer. This drift layer includes a first region having a first N type impurity concentration peak region and a second region having a second N type impurity concentration peak region that is positioned deeper than the first N type impurity concentration peak region, the second region adjoining this first region. An N+ type drain layer is formed in a surface portion of the second region.

Abstract: An image capture device capable of capturing high quality images is disclosed. The image capture device comprises a shift register, each pixel of which has a plurality of transfer electrodes extending in a direction crossing a transfer direction of information charges. A potential well formed by function of the transfer electrodes is used to store and transfer information charges generated in response to light incident on a pixel. In this image capture device, during image capture, information charges are stored in a plurality of potential wells substantially separated from each other, and, during transfer, information charges stored in at least two of the plurality of potential wells are combined by addition to be transferred.

Abstract: A solid image capturing element comprising a plurality of vertical shift registers arranged to each correspond to a column of a plurality of light receiving pixels in a matrix arrangement, a horizontal shift register provided on an output side of the plurality of vertical shift registers, and an output section provided on an output side of the horizontal shift register. In this solid image capturing element, a reverse conductive semiconductor region is formed over one major surface of one conductive semiconductor substrate, the plurality of light receiving pixels, the plurality of vertical shift registers, the horizontal shift register, and the output section are formed in the semiconductor region, and a portion of the semiconductor region where the output section is formed has a higher dopant concentration than the portion of the semiconductor region where the horizontal shift register is formed.

Abstract: A mixing of color that follows mixing of horizontally adjoining information charges corresponding to different colors is minimized during an operation for adding information charges of a plurality of pixels in a horizontal direction and during a high-speed horizontal transfer operation in a horizontal CCD shift register of a CCD image sensor. An impurity is used for forming barrier regions having a shallow channel potential among the barrier regions and storage regions that constitute transfer stages of the horizontal CCD shift register. The concentration of the impurity is established separately in a main portion, which is composed of transfer stages that are connected to the output ends of vertical CCD shift registers, and in a dummy portion, which connects the main portion with an output section and has a width that gradually decreases towards the output section. The barrier potential is therefore also established separately in the main portion and the dummy portion.

Abstract: In an image pickup apparatus in which the potential well is shifted within each light receiving pixel of a CCD image sensor during an exposure period, blooming is suppressed. The CCD image sensor has a vertical overflow drain structure in which unnecessary information charges are discharged from the charge transfer channel region according to a substrate voltage Vsub. By switching a transfer electrode of a plurality of transfer electrodes for each pixel, to which an on-voltage is applied, during the exposure period, the accumulation position of the information charges is shifted, together with the potential well, within each pixel. The amount of information charge stored in the potential well, which exceeds a predetermined upper value of amount, is discharged by applying a discharge voltage VSH, higher than a reference DC voltage VSL in a normal state, to the substrate prior to the shift of the potential well.

Abstract: An imaging system, capable of reducing blooming in a solid-state imaging device and improving image sensitivity, comprises an imaging section which has at least three transfer electrodes and is continuously arranged with pixels for producing information charges in response to the light from the outside, wherein the information charges are stored and transferred using potential wells formed by potentials applied to the transfer electrodes and, during image capture, one of the transfer electrodes is maintained in an ON state and at least another one of the transfer electrodes is alternately switched between an ON state and an OFF state. It is more preferable to average the amount of generated dark current under the transfer electrodes by switching the transfer electrodes between an ON state and an OFF state for image capture. This provides restraint of a difference in the amount of generated dark current between pixels, thus reducing image graininess.

Abstract: An image capture device capable of capturing high quality images is disclosed. The image capture device comprises a shift register, each pixel of which has a plurality of transfer electrodes extending in a direction crossing a transfer direction of information charges. A potential well formed by function of the transfer electrodes is used to store and transfer information charges generated in response to light incident on a pixel. In this image capture device, during image capture, information charges are stored in a plurality of potential wells substantially separated from each other, and, during transfer, information charges stored in at least two of the plurality of potential wells are combined by addition to be transferred.

Abstract: A solid image capturing element comprising a plurality of vertical shift registers arranged to each correspond to a column of a plurality of light receiving pixels in a matrix arrangement, a horizontal shift register provided on an output side of the plurality of vertical shift registers, and an output section provided on an output side of the horizontal shift register. In this solid image capturing element, a reverse conductive semiconductor region is formed over one major surface of one conductive semiconductor substrate, the plurality of light receiving pixels, the plurality of vertical shift registers, the horizontal shift register, and the output section are formed in the semiconductor region, and a portion of the semiconductor region where the output section is formed has a higher dopant concentration than the portion of the semiconductor region where the horizontal shift register is formed.