Patents by Inventor Yuzo Takamatsu

Yuzo Takamatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Fault test apparatus and method for testing semiconductor device under test using fault excitation function
    Patent number: 7983858
    Abstract: A fault test apparatus for testing a fault on each signal line in a circuit under test including signal lines includes a controller, which calculates a value of a fault excitation function for a fault signal line, using the fault excitation function representing a fitness result of a predetermined fault excitation condition between the fault signal line having a fault among the signal lines under test in the circuit under test and at least one of adjacent signal lines adjacent to the fault signal line and falling within a predetermined range from the fault signal line, based on layout information between the fault signal line and at least one adjacent signal line adjacent to the fault signal line, manufacturing parameter information, and timing information, and then, determines whether or not a dynamic fault is excited on the fault signal line based on the value of the fault excitation function.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: July 19, 2011
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Yuzo Takamatsu, Hiroshi Takahashi, Yoshinobu Higami, Michinobu Nakao, Takashi Aikyo, Michiaki Emori, Hideo Ohmae
  • Fault test apparatus and method for testing semiconductor device under test using fault excitation function
    Publication number: 20090063062
    Abstract: A fault test apparatus for testing a fault on each signal line in a circuit under test including signal lines includes a controller, which calculates a value of a fault excitation function for a fault signal line, using the fault excitation function representing a fitness result of a predetermined fault excitation condition between the fault signal line having a fault among the signal lines under test in the circuit under test and at least one of adjacent signal lines adjacent to the fault signal line and falling within a predetermined range from the fault signal line, based on layout information between the fault signal line and at least one adjacent signal line adjacent to the fault signal line, manufacturing parameter information, and timing information, and then, determines whether or not a dynamic fault is excited on the fault signal line based on the value of the fault excitation function.
    Type: Application
    Filed: August 21, 2008
    Publication date: March 5, 2009
    Inventors: Yuzo Takamatsu, Hiroshi Takahashi, Yoshinobu Higami, Michinobu Nakao, Takashi Aikyo, Michiaki Emori, Hideo Ohmae