Abstract: A semiconductor memory device includes a first block having a first memory cell and a second block having a second memory cell, first and second word lines respectively connected to the first and second memory cells, first and second select transistors having first ends respectively connected to the first and second word lines, a first circuit configured to apply a voltage to the first word line, and to control a gate voltage of the second select transistor, a second circuit configured to apply a voltage to the second word line, and to control a gate voltage of the first select transistor, first and second wirings respectively connected to second ends of the first and second select transistors, a third circuit configured to apply a voltage to the first wiring, and a fourth circuit configured to apply a voltage to the second wiring.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell array including a first block that includes memory cells, a second memory cell array including a second block that includes memory cells, word lines arranged in the first and second memory cell arrays, and a row decoder including transfer gates that respectively transfer voltages to the word lines. Word lines arranged in the first block include first and second groups, word lines arranged in the second block include third and fourth groups, and the first and third groups commonly use the transfer gates.

Abstract: A semiconductor memory device is provided with a plurality of memory cells connected to a plurality of word lines, a word-line leakage detector configured to detect a leakage current generated on at least one of the plurality of word lines, and a controller configured, when a leakage current is detected by the word-line leakage detector, to determine that a block including a memory cell connected to a word line through which the leakage current is flowing is defective. The word-line leakage detector has a detection voltage generator configured to generate a detection voltage in accordance with the leakage current, a comparator configured to generate a flag signal having output logic that is inverted depending on whether the detection voltage exceeds a predetermined threshold voltage, and an adjuster configured to adjust a current amount by diverting part of the leakage current in accordance with an ambient temperature.

Abstract: A semiconductor memory device is provided with a plurality of memory cells connected to a plurality of word lines, a word-line leakage detector configured to detect a leakage current generated on at least one of the plurality of word lines, and a controller configured, when a leakage current is detected by the word-line leakage detector, to determine that a block including a memory cell connected to a word line through which the leakage current is flowing is defective. The word-line leakage detector has a detection voltage generator configured to generate a detection voltage in accordance with the leakage current, a comparator configured to generate a flag signal having output logic that is inverted depending on whether the detection voltage exceeds a predetermined threshold voltage, and an adjuster configured to adjust a current amount by diverting part of the leakage current in accordance with an ambient temperature.

Abstract: A semiconductor memory device includes a plurality of memory cell data holding transistors provided in each block; a row decoder including transfer transistors, a voltage controller and a block selector in each block, the transfer transistors electrically connected to respective of the memory cell transistors, the voltage controller connected to gates of the respective transfer transistors and transferring a desired voltage to the gates of the respective transfer transistors, the block selector electrically connected to gates of the respective transfer transistors and configured to select blocks. A voltage generator generates the voltage to be supplied to the transfer transistors; and a controller controls the row decoder and the voltage generator circuit.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell array including a first block that includes memory cells, a second memory cell array including a second block that includes memory cells, word lines arranged in the first and second memory cell arrays, and a row decoder including transfer gates that respectively transfer voltages to the word lines. Word lines arranged in the first block include first and second groups, word lines arranged in the second block include third and fourth groups, and the first and third groups commonly use the transfer gates.

Abstract: A semiconductor memory device includes a plurality of memory cell data holding transistors provided in each block; a row decoder including transfer transistors, a voltage controller and a block selector in each block, the transfer transistors electrically connected to respective of the memory cell transistors, the voltage controller connected to gates of the respective transfer transistors and transferring a desired voltage to the gates of the respective transfer transistors, the block selector electrically connected to gates of the respective transfer transistors and configured to select blocks. A voltage generator generates the voltage to be supplied to the transfer transistors; and a controller controls the row decoder and the voltage generator circuit.