Patents by Inventor Yuzuru Ohji

Yuzuru Ohji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20010050389
    Abstract: A semiconductor device equipped with information storage capacitor comprising a first capacitor electrode, an oxide film, a second capacitor electrode and insulating films containing silicon as a main constituting element, wherein at least one of first and second capacitor electrodes contains as a main constituting element at least one element selected from rhodium, ruthenium, iridium, osmium and platinum, and as an adding element at least one element selected from palladium, nickel, cobalt and titanium, is excellent in adhesiveness between the capacitor electrodes and the insulating films.
    Type: Application
    Filed: March 8, 2001
    Publication date: December 13, 2001
    Inventors: Hiroshi Moriya, Tomio Iwasaki, Hiroyuki Ohta, Shinpei Iijima, Isamu Asano, Yuzuru Ohji, Yoshitaka Nakamura
  • Patent number: 6326218
    Abstract: Described is a manufacturing method of an integrated circuit which uses a thin film such as platinum or BST as a hard mask upon patterning ruthenium or the like, thereby making it possible to form a device without removing the hard mask. In addition, the invention method makes it possible to interpose a protecting film such as platinum in order to prevent, upon removing a resist used for the patterning of the hard mask, an underlying ruthenium film or the like from being damaged.
    Type: Grant
    Filed: May 22, 2000
    Date of Patent: December 4, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Yunogami, Kazuo Nojiri, Yuzuru Ohji, Sukeyoshi Tsunekawa, Masahiko Hiratani, Yuichi Matsui
  • Publication number: 20010022369
    Abstract: A steplike offset between a memory cell array region and a peripheral circuit region, which is caused by a capacitor C, is reduced by an insulating film having a thickness substantially equal to the height of the capacitor C. Wiring or interconnection grooves are defined in the neighborhood of the surface of an insulating film whose surface is flattened by a CMP method. Further, connecting holes are defined in lower portions of the bottom faces of the interconnection grooves respectively. Second layer interconnections containing copper are formed within the interconnection grooves, and connecting portions containing copper are formed within the connecting holes. The second layer interconnections and first layer interconnections are connected to each other by the connecting portions whose lengths are shortened. The second layer interconnections and the connecting portions are integrally formed by a damascene method using the CMP method.
    Type: Application
    Filed: May 15, 2001
    Publication date: September 20, 2001
    Inventors: Takuya Fukuda, Yuzuru Ohji, Nobuyoshi Kobayashi
  • Patent number: 6255151
    Abstract: A steplike offset between a memory cell array region and a peripheral circuit region, which is caused by a capacitor C, is reduced by an insulating film having a thickness substantially equal to the height of the capacitor C. Wiring or interconnection grooves are defined in the neighborhood of the surface of an insulating film whose surface is flattened by a CMP method. Further, connecting holes are defined in lower portions of the bottom faces of the interconnection grooves respectively. Second layer interconnections containing copper are formed within the interconnection grooves, and connecting portions containing copper are formed within the connecting holes. The second layer interconnections and first layer interconnections are connected to each other by the connecting portions whose lengths are shortened. The second layer interconnections and the connecting portions are integrally formed by a damascene method using the CMP method.
    Type: Grant
    Filed: December 11, 1998
    Date of Patent: July 3, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Takuya Fukuda, Yuzuru Ohji, Nobuyoshi Kobayashi
  • Patent number: 5736449
    Abstract: With recent decreases in the size of semiconductor memories, isolation problems typically arise during fabrication of a capacitor for a high-capacity semiconductor memory device. To overcome this, arrangements are provided to improve the isolation between capacitor elements even if those elements are extremely close together. For example, if a material such as platinum is used as a capacitor bottom electrode, a thin layer of titanium oxide can be deposited before forming the platinum, to provide a structure in which the titanium oxide is on the bottom portion of the trench. A high-dielectric-constant insulator is then formed over that structure by the Chemical Vapor Deposition. The high-dielectric-constant insulator has a composition which satisfies the stoichiometric composition over the platinum and which has more titanium atoms than those of the stoichiometric composition on the trench bottom.
    Type: Grant
    Filed: January 26, 1996
    Date of Patent: April 7, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Miki, Yuzuru Ohji, Shinichi Tachi
  • Patent number: 5499207
    Abstract: With recent decreases in the size of semiconductor memories, isolation problems typically arise during fabrication of a capacitor for a high-capacity semiconductor memory device. To overcome this, arrangements are provided to improve the isolation between capacitor elements even if those elements are extremely close together. For example, if a material such as platinum is used as a capacitor bottom electrode, a thin layer of titanium oxide can be deposited before forming the platinum, to provide a structure in which the titanium oxide is on the bottom portion of the trench. A high-dielectric-constant insulator is then formed over that structure by the Chemical Vapor Deposition. The high-dielectric-constant insulator has a composition which satisfies the stoichiometric composition over the platinum and which has more titanium atoms than those of the stoichiometric composition on the trench bottom.
    Type: Grant
    Filed: July 28, 1994
    Date of Patent: March 12, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Miki, Yuzuru Ohji, Shinichi Tachi
  • Patent number: 5343353
    Abstract: A microminiature, large capacitor for a semiconductor memory is formed from a raw material compound of plural different kinds of metal atoms for deposition, irrespective of the material, temperature and surface condition of a substrate, thereby forming a thin dielectric film having uniform characteristics not affected by the interface even though the film is made as thin as approximately 0.1 .mu.m. The microminiature large capacitance capacitor has a capacitance unaffected by an oxide existing at the interface between a ferroelectric and electrodes without using precious metals such as platinum having the least degree of freedom in deposition of thin films and microminiature processing. The ferroelectric thin film is deposited using an organic metal comprising a plurality of kinds of metal elements in conformity with the composition of a desired dielectric. As electrodes for use in forming a capacitor, a substance exhibiting conductivity after oxidation is preferably employed.
    Type: Grant
    Filed: August 17, 1992
    Date of Patent: August 30, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Miki, Yuzuru Ohji, Shinichi Tachi, Keiichi Kanehori
  • Patent number: 5188976
    Abstract: Before a high permittivity interlayer insulating film of a non-volatile memory having a two-level gate electrode structure, a surface of a substrate in a peripheral circuit MOS area is successively covered with a thermal oxide film and a polycrystalline silicon film. Before the interlayer insulating film is selectively removed on the peripheral circuit MOS area, the surface of the interlayer insulating film of the non-volatile memory is covered with a polycrystalline silicon film. When the interlayer insulating film in the peripheral circuit MOS area is removed, the polycrystalline silicon film as a lower layer in the peripheral circuit area serves as a buffer layer against contamination or damage due to the etching, and the conductive layer on the surface of the interlayer insulating film in the non-volatile memory portion also serves as a buffer layer against the contamination or damage due to the etching.
    Type: Grant
    Filed: July 9, 1991
    Date of Patent: February 23, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Hitoshi Kume, Tetsuo Adachi, Yuzuru Ohji, Tokuo Kure, Masahiro Ushiyama, Hiroshi Kawakami
  • Patent number: 4907046
    Abstract: A solid state device includes a transistor (A) and a capacitor (B). The capacitor is defined by a lower polycrystalline silicon layer or electrode (20), multiple dielectric layers (22), and an upper polycrystalline silicon layer or electrode (30). The dielectric layers are formed by vapor depositing a 3.6-18.6 nm thick layer of silicon nitride on the lower polycrystalline layer. Thicker silicon nitride layers increase the failure rate and decrease the capacitance (FIG. 8). More specifically, the silicon nitride layer is deposited on a thin, about 1 nm, oxidized film or surface (24) of the polycrystalline silicon layer. The silicon nitride layer is oxidized forming a silicon dioxide layer (28) until the silicon nitride layer is only about 3 nm thick. This forms on oxide layer that is 1-8.4 nm thick. If the silicon nitride layer is reduced below 3 nm, the polycrystalline silicon tends to oxidize rapidly reducing capacitance and increasing failure (FIG. 8).
    Type: Grant
    Filed: March 15, 1988
    Date of Patent: March 6, 1990
    Assignee: Hitachi Ltd.
    Inventors: Yuzuru Ohji, Osamu Kasahara, Yoshitaka Tadaki, Hiroko Kaneko, Toshiyuki Mine, Kunihiro Yagi
  • Patent number: 4563900
    Abstract: In an acoustic microscope wherein an acoustic wave is projected to a predetermined specimen by an acoustic lens, and a disturbed acoustic wave from the specimen is imaged; an acoustic microscope characterized in that the lens has a ring which is arranged around it, whereby a liquid to serve as an acoustic propagation medium is held between the ring and the specimen by capillarity.
    Type: Grant
    Filed: April 26, 1984
    Date of Patent: January 14, 1986
    Assignee: Hitachi, Ltd.
    Inventors: Kunio Harada, Sumio Yamaguchi, Hiroshi Kanda, Isao Ishikawa, Yuzuru Ohji