Abstract: The invention relates to an optoelectronic device comprising a photonic interposer comprising: a photonic circuit containing at least one active optical component, an upper interconnect layer comprising at least one upper control portion, a lower interconnect layer comprising at least one lower control portion and lower intermediate portions, at least one TSV directly connecting the upper control portion to the lower control portion, conductive vias connecting the lower intermediate portions to the active optical component; at least one first microelectronic chip joined to the upper face of the photonic interposer; a second microelectronic chip joined to the lower face of the photonic interposer, and connected to the lower control portion and to the lower intermediate portions.

Abstract: The invention relates to an optoelectronic device 1 comprising: a photonic interposer 10 comprising: a photonic circuit 14.1 containing at least one active optical component 14.2, an upper interconnect layer 11, comprising at least one upper control portion 11.2, a lower interconnect layer 17, comprising at least one lower control portion 17.2, and lower intermediate portions 17.3, at least one TSV 18.1 directly connecting the upper control portion 11.2 to the lower control portion 17.2, conductive vias 15.1 connecting the lower intermediate portions 17.3 to the active optical component 14.2; at least one first microelectronic chip 20, joined to the upper face 10a of the photonic interposer; a second microelectronic chip 30, joined to the lower face 10b of the photonic interposer, and connected to the lower control portion 17.2 and to the lower intermediate portions 17.3.

Abstract: The present invention involves a method of controlling at least one first element (22) for heating a multi-resonant optical device (10), automatically alternating between at least a first mode and a second mode, wherein, in the first mode, the first heating element is controlled by a first feedback loop (20) to lead the optical device to operate at a first resonance peak and wherein, at least during part of the second mode, the first feedback loop is made diverging to lead the optical device to operate at a second resonance peak.

Abstract: An optical receiver adapted to convert a received optical signal into a phase change of a timing signal to generate a first modified timing signal and to generate a data signal by comparing the first modified timing signal with a reference signal.

Abstract: An optical receiver adapted to convert a received optical signal into a phase change of a timing signal to generate a first modified timing signal and to generate a data signal by comparing the first modified timing signal with a reference signal.

Abstract: A method and device for digital data processing based on a data flow processing model is suitable for the execution, in a distributed manner on multiple calculation nodes, of multiple data processing operations modelled by directed graphs, where two different processing operations include at least one common calculation node. The device includes an identification processor configured to, from a valued directed multi-graph made up of the union of several distinct processing graphs and divided into several valued directed sub-multi-graphs, called chunks, and whose input and output nodes are buffer memory nodes of the multi-graph, identify a coordination module for each chunk. Furthermore each identified coordination module is configured to synchronize portions of processing operations that are to be executed in the chunk with which the respective coordination module is associated, independently of portions of processing operations that are to be executed in other chunks.

Abstract: An optical network including: a medium; at least one beam of optical waveguides extending over the medium; for each beam, interfaces between the beam and the processing units, respectively. The beam successively links the interfaces in a closed loop oriented in a certain direction of rotation of information. The communication units of each interface are transversely arranged in ranks increasing from the periphery to the interior of the beam. First and second optical waveguides start from different interfaces or end at different interfaces. The first optical waveguide links two communication units both of them readers and/or writers of different ranks in first and second respective interfaces. The second optical waveguide passes through a communication unit from the second interface of lower rank to that of the communication unit of said second interface through which the first optical waveguide passes.

Abstract: A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference (“BGPD”) of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently.

Abstract: An asynchronous integrated circuit is designed from a library of cells comprising at least one cell having parameters of signal propagation between a first terminal and a second terminal and between the second terminal and a third terminal depending on the parameter of signal propagation between the first and the third terminal. A synchronous integrated circuit corresponding to the asynchronous integrated circuit is synthesized using said cell to represent a portion of the asynchronous circuit, said cell being rated by a dummy clock signal. The synthesized integrated circuit is verified using the parameter of signal propagation between the first terminal and the third terminal to simulate the operation of said portion of the asynchronous circuit.

Abstract: An optical arbiter device, between conflicting access requests to a shared resource sent by N processing nodes of a network-on-chip system, comprising at least one primary optical arbiter bus, at least one optical source for transmitting a first optical signal in said at least one primary optical arbiter bus, and a sequence of N optical arbiter cells coupled with the primary optical arbiter bus, each of these optical arbiter cells being associated with a processing node and having means for selecting the processing node with which said each optical arbiter cell is associated by re-routing the first optical signal. The optical source is designed to transmit a second optical signal propagated in an opposite direction to the first optical signal along the primary optical arbiter bus. Furthermore, the selection means of each optical arbiter cell are designed to perform said selection by re-routing the first and second optical signals.

Abstract: The present invention involves a method of controlling at least one first element (22) for heating a multi-resonant optical device (10), automatically alternating between at least a first mode and a second mode, wherein, in the first mode, the first heating element is controlled by a first feedback loop (20) to lead the optical device to operate at a first resonance peak and wherein, at least during part of the second mode, the first feedback loop is made diverging to lead the optical device to operate at a second resonance peak.

Abstract: An optical arbiter device, between conflicting access requests to a shared resource sent by N processing nodes of a network-on-chip system, comprising at least one primary optical arbiter bus, at least one optical source for transmitting a first optical signal in said at least one primary optical arbiter bus, and a sequence of N optical arbiter cells coupled with the primary optical arbiter bus, each of these optical arbiter cells being associated with a processing node and having means for selecting the processing node with which said each optical arbiter cell is associated by re-routing the first optical signal. The optical source is designed to transmit a second optical signal propagated in an opposite direction to the first optical signal along the primary optical arbiter bus. Furthermore, the selection means of each optical arbiter cell are designed to perform said selection by re-routing the first and second optical signals.

Abstract: An optical network including: a medium; at least one beam of optical waveguides extending over the medium; for each beam, interfaces between the beam and the processing units, respectively. The beam successively links the interfaces in a closed loop oriented in a certain direction of rotation of information. The communication units of each interface are transversely arranged in ranks increasing from the periphery to the interior of the beam. First and second optical waveguides start from different interfaces or end at different interfaces. The first optical waveguide links two communication units both of them readers and/or writers of different ranks in first and second respective interfaces. The second optical waveguide passes through a communication unit from the second interface of lower rank to that of the communication unit of said second interface through which the first optical waveguide passes.

Abstract: The invention relates to a rocket engine with an extendable divergent which includes an exhaust nozzle for the gases coming from a combustion chamber, the nozzle having a longitudinal axis (ZZ?) including a first portion defining a nozzle throat and a first fixed divergent section (12), at least one second extendable divergent section (16) with a larger cross-section than the first fixed divergent section (12) and a mechanism (18) for extending the second extendable divergent section (16) arranged outside the first and second divergent sections (12, 16). A rigid thermal protection screen (102) is positioned between the extending mechanism (18) and the first fixed divergent section (12). The thermal protection screen (102) has a convex wall (104) on the surface thereof that faces the first fixed divergent section (12).

Abstract: An integrated with a block including first and second oppositely doped semiconductor wells. There are standard cells placed next to one another, each standard cell including first transistors and a clock tree cell encircled by standard cells. The clock tree cell has a third semiconductor well with the same doping type as the doping of the first well and second transistors. The clock tree cell also has a semiconductor strip extending continuously around the third well and having the opposite doping type to the doping of the third well to electrically isolate the third well from the first well.

Abstract: The invention relates to an integrated circuit comprising: a first semiconductor well (60); a plurality of standard cells (66), each standard cell comprising a first field-effect transistor in FDSOI technology comprising a first semiconductor ground plane located immediately on the first well; and a clock tree cell (30) contiguous with the standard cells, the clock tree cell comprising a second field-effect transistor in FDSOI technology, which transistor comprises a second semiconductor ground plane located immediately on the first well (60), so as to form a p-n junction with this first well. The integrated circuit comprises an electrical power supply network (51) able to apply separate electrical biases directly to the first and second ground planes.

Abstract: A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference (“BGPD”) of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently.

Abstract: The invention relates to an integrated circuit comprising: a block comprising: first (38) and second (40) oppositely doped semiconductor wells; standard cells (42, 43) placed next to one another, each standard cell (42) comprising first transistors (60, 62), and a clock tree cell (30) encircled by standard cells, the clock tree cell (30) comprising: a third semiconductor well (104) having the same doping type as the doping of the first well (38); second transistors (100, 102); a semiconductor strip (106) extending continuously around the third well (104), and having the opposite doping type to the doping of the third well, so as to electrically isolate the third well (104) from the first well (38).

Abstract: The invention relates to an integrated circuit comprising: a first semiconductor well (60); a plurality of standard cells (66), each standard cell comprising a first field-effect transistor in FDSOI technology comprising a first semiconductor ground plane located immediately on the first well; and a clock tree cell (30) contiguous with the standard cells, the clock tree cell comprising a second field-effect transistor in FDSOI technology, which transistor comprises a second semiconductor ground plane located immediately on the first well (60), so as to form a p-n junction with this first well. The integrated circuit comprises an electrical power supply network (51) able to apply separate electrical biases directly to the first and second ground planes.

Abstract: This device (10) for digital data processing based on a data flow processing model is suitable for the execution, in a distributed manner on multiple calculation nodes (16, 18, 20, 24, 26, 28, 30, 34, 36, 38, 44, 48), of multiple data processing operations modelled by directed graphs, where two different processing operations can include at least one common calculation node (16, 20, 26, 28, 30, 34, 36, 38). It includes means (12) for the identification, from a valued directed multi-graph made up of the union of several distinct processing graphs and divided into several valued directed sub-multi-graphs (54, 56, 58), called chunks, and whose input and output nodes are buffer memory nodes of the multi-graph, of a coordination module (16, 26, 34) for each chunk.