Patents by Inventor Yvan Morandini

Yvan Morandini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220076993
    Abstract: The present disclosure relates to a multilayer semiconductor-on-insulator structure, comprising, successively from a rear face toward a front face of the structure: a semiconductor carrier substrate with high electrical resistivity, whose electrical resistivity is between 500 ?·cm and 30 k?·cm, a first electrically insulating layer, an intermediate layer, a second electrically insulating layer, which has a thickness less than that of the first electrically insulating layer, an active semiconductor layer, the multilayer structure comprises: at least one FD-SOI region, in which the intermediate layer is an intermediate first semiconductor layer, at least one RF-SOI region, adjacent to the FD-SOI region, in which the intermediate layer is a third electrically insulating layer, the RF-SOI region comprising at least one radiofrequency component plumb with the third electrically insulating layer.
    Type: Application
    Filed: December 23, 2019
    Publication date: March 10, 2022
    Inventors: Yvan Morandini, Walter Schwarzenbach, Frédéric Allibert, Eric Desbonnets, Bich-Yen Nguyen
  • Publication number: 20220076992
    Abstract: A semiconductor-on-insulator multilayer structure, comprises: —a stack, called the back stack, of the following layers from a back side to a front side of the structure: a semiconductor carrier substrate the electrical resistivity of which is between 500 ?·cm and 30 k?·cm, a first electrically insulating layer, a first semiconductor layer, —at least one trench isolation that extends through the back stack at least down to the first electrically insulating layer), and that electrically isolates two adjacent regions of the multilayer structure, the multilayer structure being characterized in that it further comprises at least one FD-SOI first region, and at least one RF-SOI second region.
    Type: Application
    Filed: December 23, 2019
    Publication date: March 10, 2022
    Applicant: Soitec
    Inventors: Yvan Morandini, Walter Schwarzenbach, Frédéric Allibert, Eric Desbonnets, Bich-Yen Nguyen
  • Patent number: 9077282
    Abstract: A variable capacitance device including: first and second transistors coupled in series by their main current nodes between first and second nodes of the device, a control node of the first transistor being adapted to receive a first control signal, and a control node of the second transistor being adapted to receive a second control signal; and control circuitry adapted to generate the first and second control signals from a selection signal.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: July 7, 2015
    Assignees: STMicroelectronics S.A., International Business Machines Corporation
    Inventors: Yvan Morandini, Romain Debrouke
  • Patent number: 8981529
    Abstract: A variable capacitance device including: first and second transistors coupled in parallel between first and second nodes of the capacitive device, a control node of the first transistor being adapted to receive a control signal, and a control node of the second transistor being adapted to receive the inverse of the control signal, wherein the first and second transistors are formed in a same semiconductor well.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: March 17, 2015
    Assignees: STMicroelectronics SA, International Business Machines Corporation
    Inventors: Yvan Morandini, Romain Debrouke