Abstract: Method for verifying data generated by an electronic device included in equipment, the electronic device including a computing unit, a one-time programmable memory and a volatile memory, the equipment including a rewritable non-volatile memory and a communication bus enabling the electronic device to store data in the rewritable non-volatile memory. The method includes: creating a secured channel by encryption between the equipment and a server; obtaining an authentication key from the server; loading data and a message authentication code from the rewritable non-volatile memory to the volatile memory, the message authentication code obtained by the electronic device from the authentication key and said data prior to the storage of said data and message authentication code in the rewritable non-volatile memory, the electronic device not having kept the authentication key following the obtaining of the message authentication code; verifying said data using the secret key and the message authentication code.

Abstract: Method for verifying data generated by an electronic device included in equipment, the electronic device including a computing unit, a one-time programmable memory and a volatile memory, the equipment including a rewritable non-volatile memory and a communication bus enabling the electronic device to store data in the rewritable non-volatile memory. The method includes: creating a secured channel by encryption between the equipment and a server; obtaining an authentication key from the server; loading data and a message authentication code from the rewritable non-volatile memory to the volatile memory, the message authentication code obtained by the electronic device from the authentication key and said data prior to the storage of said data and message authentication code in the rewritable non-volatile memory, the electronic device not having kept the authentication key following the obtaining of the message authentication code; verifying said data using the secret key and the message authentication code.

Abstract: The invention relates to a method for managing the endurance of a data storage system provided with a set of sectors endowed with a guaranteed native endurance capacity (G), comprising the steps consisting in: —partitioning said data storage system into a plurality of work sectors, and into a plurality of replacement sectors able to form an endurance reservoir, certain of the work sectors being intended to be replaced by replacement sectors when said work sectors are expended after a certain number of programming and/or erasure cycles; —defining an address management area making it possible to retrieve the location of the replacement sectors assigned to expended work sectors; —determining, sector by sector, whether a current work sector is physically expended, and executing a step of replacing this work sector by a replacement sector, only when said current work sector is declared physically expended.

Abstract: A data storage device may include one or more pages, each page having a fixed number of memory cells, each memory cell being adapted to store one unit of data; a verification page, the verification page having a corresponding fixed number of verification cells, each verification cell storing a predetermined value; and a controller configured to 1) receive a read command having an address value, and 2) upon receiving the read command, a) retrieve a predetermined value from a verification cell corresponding to the address value, b) determine whether the retrieved predetermined value is an expected value, and c) if so, providing a retrieved unit of data, and if not, initiating a protective action. Determining whether the retrieved predetermined value is the expected value may include applying a function to the address value to obtain a result and determining whether the result corresponds to the retrieved predetermined value.

Abstract: The invention relates to a method for managing the endurance of a data storage system provided with a set of sectors endowed with a guaranteed native endurance capacity (G), comprising the steps consisting in:—partitioning said data storage system into a plurality of work sectors, and into a plurality of replacement sectors able to form an endurance reservoir, certain of the work sectors being intended to be replaced by replacement sectors when said work sectors are expended after a certain number of programming and/or erasure cycles;—defining an address management area making it possible to retrieve the location of the replacement sectors assigned to expended work sectors;—determining, sector by sector, whether a current work sector is physically expended, and executing a step of replacing this work sector by a replacement sector, only when said current work sector is declared physically expended.

Abstract: A content-addressable memory (CAM) for managing the reallocation of erasable objects within a non-volatile memory is conceptually separated into two tables: a first table provides verification of whether or not a logical address has been reallocated and, if so, a second table provides the physical address of the reallocated erasable object.

Abstract: In a device having a plurality of circuits that can store at least a first value and a second value, a method can include configuring at least one circuit to persistently store the first value; determining whether the at least one circuit is storing the second value; and initiating a countermeasure if the at least one circuit is storing the second value. Determining whether the at least one circuit is storing the second value can include detecting whether the device has been attacked. Non-limiting examples of initiating a countermeasure can include resetting a portion of the device, powering down a portion of the device, activating an alarm circuit, causing protected data stored in the device to be erased, causing portions of the device to self-destruct, or causing the device to not respond to input applied to the interface.

Abstract: A subset of software objects stored in a first segment of non-volatile memory are identified as requiring frequent write operations or otherwise associated with a high endurance requirement. The subset of software objects are move to a second segment of non-volatile memory with a high endurance capacity, due to the application of wear leveling techniques to the second segment of non-volatile memory. The first and second segments of memory can be located in the same memory device or different memory devices.

Abstract: Techniques for coding and decoding redundant coding for column defects cartography. Defective cell groups identified in a memory array are redundantly encoded with a different bit pattern than the bit pattern used for functional cell groups. The identified defective cell groups are repaired using redundant cell groups in the memory array. The defective cell groups are later re-identified by checking the redundant bit pattern encoded in the cell groups. If new defective cell groups are identified, the memory array is identified as failing. If no new defective cell groups are identified, the memory array is identified as passing, and the identified defective cell groups are repaired.

Abstract: A method and system for checking data stored in a memory of in a computer system is disclosed. The memory includes a plurality of memory addresses. The method and system include providing a signature generator coupled with the memory, providing a checker memory coupled with the signature generator and separate from the memory, and providing an address remapper coupled with the checker memory and the memory. The signature generator provides at least one signature corresponding to the data, which resides in a protection window of the memory. The protection window includes at least one memory address of the plurality of memory addresses. The checker memory stores the at least one signature in at least one checker address, which corresponds to the at least one memory address. The address remapper for translates between the at least one memory address and the at least one checker address.

Abstract: A subset of software objects stored in a first segment of non-volatile memory are identified as requiring frequent write operations or otherwise associated with a high endurance requirement. The subset of software objects are move to a second segment of non-volatile memory with a high endurance capacity, due to the application of wear leveling techniques to the second segment of non-volatile memory. The first and second segments of memory can be located in the same memory device or different memory devices.

Abstract: A content-addressable memory (CAM) for managing the reallocation of erasable objects within a non-volatile memory is conceptually separated into two tables: a first table provides verification of whether or not a logical address has been reallocated and, if so, a second table provides the physical address of the reallocated erasable object.

Abstract: A data storage device may include one or more pages, each page having a fixed number of memory cells, each memory cell being adapted to store one unit of data; a verification page, the verification page having a corresponding fixed number of verification cells, each verification cell storing a predetermined value; and a controller configured to 1) receive a read command having an address value, and 2) upon receiving the read command, a) retrieve a predetermined value from a verification cell corresponding to the address value, b) determine whether the retrieved predetermined value is an expected value, and c) if so, providing a retrieved unit of data, and if not, initiating a protective action. Determining whether the retrieved predetermined value is the expected value may include applying a function to the address value to obtain a result and determining whether the result corresponds to the retrieved predetermined value.

Abstract: Techniques for coding and decoding redundant coding for column defects cartography. Defective cell groups identified in a memory array are redundantly encoded with a different bit pattern than the bit pattern used for functional cell groups. The identified defective cell groups are repaired using redundant cell groups in the memory array. The defective cell groups are later re-identified by checking the redundant bit pattern encoded in the cell groups. If new defective cell groups are identified, the memory array is identified as failing. If no new defective cell groups are identified, the memory array is identified as passing, and the identified defective cell groups are repaired.

Abstract: In a device having a plurality of circuits that can store at least a first value and a second value, a method can include configuring at least one circuit to persistently store the first value; determining whether the at least one circuit is storing the second value; and initiating a countermeasure if the at least one circuit is storing the second value. Determining whether the at least one circuit is storing the second value can include detecting whether the device has been attacked. Non-limiting examples of initiating a countermeasure can include resetting a portion of the device, powering down a portion of the device, activating an alarm circuit, causing protected data stored in the device to be erased, causing portions of the device to self-destruct, or causing the device to not respond to input applied to the interface.

Abstract: A method and system for checking data stored in a memory of in a computer system is disclosed. The memory includes a plurality of memory addresses. The method and system include providing a signature generator coupled with the memory, providing a checker memory coupled with the signature generator and separate from the memory, and providing an address remapper coupled with the checker memory and the memory. The signature generator provides at least one signature corresponding to the data, which resides in a protection window of the memory. The protection window includes at least one memory address of the plurality of memory addresses. The checker memory stores the at least one signature in at least one checker address, which corresponds to the at least one memory address. The address remapper for translates between the at least one memory address and the at least one checker address.