Patents by Inventor Yves Jean Chabal

Yves Jean Chabal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180274097
    Abstract: Described herein are methods for forming a conformal Group 4, 5, 6, 13 metal or metalloid doped silicon nitride film. In one aspect, there is provided a method of forming an aluminum silicon nitride film comprising the steps of: providing a substrate in a reactor; introducing into the reactor an at least one aluminum precursor which reacts on at least a portion of the surface of the substrate to provide a chemisorbed layer; purging the reactor with a purge gas; introducing into the reactor an organoaminosilane precursors to react on at least a portion of the surface of the substrate to provide a chemisorbed layer; introducing a nitrogen source and an inert gas into the reactor to react with at least a portion of the chemisorbed layer; and optionally purge the reactor with an inert gas; and wherein the steps are repeated until a desired thickness of the aluminum nitride film is obtained.
    Type: Application
    Filed: October 6, 2016
    Publication date: September 27, 2018
    Inventors: Xinjian LEI, Moo-Sung KIM, Anupama MALLIKARJUNAN, Aaron Michael DANGERFIELD, Luis Fabián PEÑA, Yves Jean CHABAL
  • Patent number: 6723581
    Abstract: The present invention provides a method of manufacturing a semiconductor device comprising, providing a semiconductor substrate, forming a substantially-hydroxylated SiOxHy layer on the semiconductor substrate in a presence of oxygen and hydrogen, and forming a metallic oxide, high-K dielectric layer on the substantially-hydroxylated SiOxHy layer. The substantially-hydroxylated SiOxHy layer has a surface concentration of hydroxyl (OH) species equal to or greater than about 3×1014 hydroxyl per cm2.
    Type: Grant
    Filed: October 21, 2002
    Date of Patent: April 20, 2004
    Assignee: Agere Systems Inc.
    Inventors: Yves Jean Chabal, Martin Laurence Green, Glen David Wilk
  • Patent number: 6388290
    Abstract: An integrated circuit comprising active and passive devices is formed in a thin slice of monocrystalline semiconductor bonded to a high resistivity polycrystalline silicon substrate. As compared with conventional integrated circuits supported on a monocrystalline substrate, circuits in monocrystalline films bonded to high resistivity polycrystalline substrates are less subject to parasitic capacitance, crosstalk and eddy currents. As compared with typical SOI wafers, the polycrystalline substrates have higher resistivity, and this resistivity is much less affected by contamination than it would be in monocrystalline substrates. Compared to silicon-on-sapphire or silicon on any other insulating material, the polycrystalline substrates are more compatible with the mechanical, thermal, and optical properties of the crystalline silicon layer.
    Type: Grant
    Filed: June 10, 1998
    Date of Patent: May 14, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: George K. Celler, Yves Jean Chabal