Abstract: An electronic circuit includes at least one first multi-gate transistor including a first gate and a second gate different from the first gate; and a regulation unit designed to measure a variable representing the drain-source voltage of the first transistor and to apply a polarization potential as a function of the variable to the second gate of the first transistor.

Abstract: A differential-logic logic circuit chained with another differential-logic circuit comprises a first logic cell composed of back-gate transistors, the first cell having a first input for receiving a first input signal and having an output for delivering a first output signal, and a second logic cell complementary to the first cell, composed of back-gate transistors, the second cell having as many inputs as the first cell, each input able to receive an input signal complementary to the respective input signal of the first cell, the second cell having an output for delivering a second output signal complementary to the first output signal of the first cell. The first output signal of the first cell is applied to the back gate of each transistor of the second cell, and the second output signal of the second cell is applied to the back gate of each transistor of the first cell.

Abstract: An electronic circuit includes at least one first multi-gate transistor including a first gate and a second gate different from the first gate; and a regulation unit designed to measure a variable representing the drain-source voltage of the first transistor and to apply a polarization potential as a function of the variable to the second gate of the first transistor.

Abstract: A differential-logic logic circuit chained with another differential-logic circuit comprises a first logic cell composed of back-gate transistors, the first cell having a first input for receiving a first input signal and having an output for delivering a first output signal, and a second logic cell complementary to the first cell, composed of back-gate transistors, the second cell having as many inputs as the first cell, each input able to receive an input signal complementary to the respective input signal of the first cell, the second cell having an output for delivering a second output signal complementary to the first output signal of the first cell. The first output signal of the first cell is applied to the back gate of each transistor of the second cell, and the second output signal of the second cell is applied to the back gate of each transistor of the first cell.

Abstract: A packaged semiconductor device (200) with a substrate (220) having, sandwiched in an insulator (221), a flat sheet-like sieve member (240) made of a non-linear material switching from insulator to conductor mode at a preset voltage. Both member surfaces are free of indentations; the member is perforated by through-holes, which are grouped into a first set (241) and a second set (242). Metal traces (251) over one member surface are positioned across the first set through-holes (241); each trace is connected to a terminal on the substrate top and, through the hole, to a terminal on the substrate bottom. Analogous for metal traces (252) over the opposite member surface and second set through-holes (242). Traces (252) overlap with a portion of traces (252) to form the locations for the conductivity switches, creating local ultra-low resistance bypasses to ground for discharging overstress events.

Abstract: A packaged semiconductor device (200) with a substrate (220) having, sandwiched in an insulator (221), a flat sheet-like sieve member (240) made of a non-linear material switching from insulator to conductor mode at a preset voltage. Both member surfaces are free of indentations; the member is perforated by through-holes, which are grouped into a first set (241) and a second set (242). Metal traces (251) over one member surface are positioned across the first set through-holes (241); each trace is connected to a terminal on the substrate top and, through the hole, to a terminal on the substrate bottom. Analogous for metal traces (252) over the opposite member surface and second set through-holes (242). Traces (252) overlap with a portion of traces (252) to form the locations for the conductivity switches, creating local ultra-low resistance bypasses to ground for discharging overstress events.

Abstract: A system comprising a first layer comprising one or more metal sub-layers and a protective overcoat (PO) layer adjacent to the first layer. The PO layer is adapted to protect the first layer, and a circuit logic is at least partially embedded within the PO layer. The circuit logic couples to one of the metal sub-layers.

Abstract: A packaged semiconductor device (200) with a substrate (220) having, sandwiched in an insulator (221), a flat sheet-like sieve member (240) made of a non-linear material switching from insulator to conductor mode at a preset voltage. Both member surfaces are free of indentations; the member is perforated by through-holes, which are grouped into a first set (241) and a second set (242). Metal traces (251) over one member surface are positioned across the first set through-holes (241); each trace is connected to a terminal on the substrate top and, through the hole, to a terminal on the substrate bottom. Analogous for metal traces (252) over the opposite member surface and second set through-holes (242). Traces (252) overlap with a portion of traces (252) to form the locations for the conductivity switches, creating local ultra-low resistance bypasses to ground for discharging overstress events.

Abstract: A CMOS bus receiver for converting a reduced voltage swing input signal at an input node to a higher voltage swing output signal at an output node. The receiver includes a first and a second MOS transistor connected in series by their source and drain between a first side and a second side of a power supply, a gate of the first MOS transistor being connected to the input node, the common connection node of the first and second MOS transistors being connected to the output node. A third and a fourth MOS transistor connected in series by their source and drain between the first side of the power supply and the input node are also provided, a gate of the third MOS transistor being connected to the output node, and a gate of the second MOS transistor being connected to the common connection node of the third and fourth MOS transistors.

Abstract: A CMOS bus receiver for converting a reduced voltage swing input signal at an input node to a higher voltage swing output signal at an output node. The receiver includes a first and a second MOS transistor connected in series by their source and drain between a first side and a second side of a power supply, a gate of the first MOS transistor being connected to the input node, the common connection node of the first and second MOS transistors being connected to the output node. A third and a fourth MOS transistor connected in series by their source and drain between the first side of the power supply and the input node are also provided, a gate of the third MOS transistor being connected to the output node, and a gate of the second MOS transistor being connected to the common connection node of the third and fourth MOS transistors.

Abstract: A bus (10) uses DS encoding with an additional wire framing the signal on the Data and Strobe lines, allocating control of the lines by a master (12) or a selected slave (14). A data clock can be recovered from the Data and Strobe lines, eliminating clock skew between circuits. Slaves (14) with differing speed abilities are supported by generating an address portion of the message at a first speed and the remaining transaction portion at the full capabilities of the selected slave. Further, the slaves (14) can adapt their bus drivers to various voltage levels to accommodate master circuits using different processing technologies. The bus (10) is scalable to allow high bandwidths.

Abstract: An oscillator includes a resonator, such as a crystal (12) coupled to first and second capacitor banks (14). The first and second capacitor banks (14) each comprise a plurality of capacitors (16) coupled to the resonator (12) through respective switching devices (18) that may be selectively enabled. The switches (18) are selectively enabled to couple a desired set of said capacitors (16) to said resonator (12). At least one of the switches (18sd) is controlled with a clock signal having a programmable duty cycle from a sigma-delta modulator (20) to enable at least one of said capacitors (16sd) during a first phase of the clock signal and disable that capacitor (16sd) during a second phase of the clock signal.

Abstract: This invention relates to a high-resolution digital/analogue converter intended in particular for the tuning of a voltage-controlled quartz oscillator. This converter comprises a first second-order Sigma-Delta modulator (1) to the output of which is connected the input of a second Sigma-Delta modulator (9) producing a single bit at its output and a digital/analogue conversion circuit (13). The circuit of the converter furthermore comprises means for filtering the high-frequency components of the signal undergoing processing so as to obtain a quasi-stable D.C. voltage source with a high resolution.This invention is applicable to any voltage-controlled system having large inertia, and in particular, voltage-controlled quartz oscillators and transducers.

Abstract: Digital-analog converter intended to convert into analog signals digital signals formed of sign bits, of step bits and of segment bits, particularly signals coded by data compression according to law A, the said converter comprising a sign generator (4), intended to receive the sign bit of the said digital signal, a step generator (7), connected to the output of the sign generator and intended to receive the step bits of the said digital signal and to a segment generator (8) connected to the step generator and intended to receive the segment bits of the said digital signal, characterized in that the segment generator (8) is connected to the sign generator by means of the step generator (7) only.

Abstract: The method includes generating a binary signal (S4A to S4D) which is time modulated. To do this, an alternating signal (S1) is compared with a known cyclical signal (S5) and a threshold signal. There is measured the durations between the transitions of the modulated signal by means of a high speed clock and by means of counting in the positive and negative directions of the clock pulses for one or more periods of the signal under examination. If, after counting, a residual value is found, one generates a binary signal representing the transition.