Abstract: A processing engine, such as a digital signal processor, includes an execution mechanism, a repeat count register and a repeat count index register. The execution mechanism is operable for a repeat instruction to initialize the repeat count index register with the content of the repeat count register, and to modify the content of the repeat count register. The repeat instruction comprises two parts, the first of which initializes the repeat count index register and initiates repeat of a subsequent instruction, and the second part of which modifies the content of the repeat count register.

Abstract: A processor (100) is provided that is a programmable fixed point digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The processor includes an instruction buffer unit (106), a program flow control unit (108), an address/data flow unit (110), a data computation unit (112), and multiple interconnecting busses. Dual multiply-accumulate blocks improve processing performance. A memory interface unit (104) provides parallel access to data and instruction memories. The instruction buffer is operable to buffer single and compound instructions pending execution thereof. A decode mechanism is configured to decode instructions from the instruction buffer. The use of compound instructions enables effective use of the bandwidth available within the processor.

Abstract: A processing engine, such as a digital signal processor, includes an execution mechanism, a repeat count register and a repeat count index register. The execution mechanism is operable for a repeat instruction to initialize the repeat count index register with the content of the repeat count register, and to modify the content of the repeat count register. The repeat instruction comprises two parts, the first of which initializes the repeat count index register and initiates repeat of a subsequent instruction, and the second part of which modifies the content of the repeat count register.

Abstract: An electronic device for transferring data between a serial port and a memory of a CPU is provided having a plurality of data registers for transferring data between said serial port and said memory in response to a first set of control signals, a data bus connected to said registers and said memory for passing data to and from said memory in response to a portion of said first set of control signals, first control circuitry for generating said first set of control signals and for generating at least one interrupt to said CPU, at least one control register connected to said first control circuitry for providing mode control information to said first control circuitry, a plurality of address registers for storing data address, at least one address generator connected to said address registers for automatically generating addresses in response to a second set of control signals, an address bus connected to said address registers, and second control circuitry connected to said address generator, a portion of sai