Abstract: An integrated circuit includes two or more communication controllers and a plurality of point to point serial communication lanes for communication external to the integrated circuit. A programmable cross-point circuit allows different sets of serial communication lanes to be coupled at different times to the communication controllers in order to optimize performance of different applications.

Abstract: A network of processing devices includes a medium for low-latency interfaces for providing point-to-point connections between each of the processing devices. A switch within each processing device is arranged to facilitate communications in any combination between the processing resources and the local point-to-point interfaces within each processing device. A networking layer is provided above the low-latency interface stack, which facilitates re-use of software and exploits existing protocols for providing the point-to-point connections. Higher speeds are achieved for switching between the relatively low numbers of processor resources within each processing device, while low-latency point-to-point communications are achieved using the low-latency interfaces for accessing processor resources that are external to a processing device.

Abstract: A network of processing devices includes a medium for low-latency interfaces for providing point-to-point connections between each of the processing devices. A switch within each processing device is arranged to facilitate communications in any combination between the processing resources and the local point-to-point interfaces within each processing device. A networking layer is provided above the low-latency interface stack, which facilitates re-use of software and exploits existing protocols for providing the point-to-point connections. Higher speeds are achieved for switching between the relatively low numbers of processor resources within each processing device, while low-latency point-to-point communications are achieved using the low-latency interfaces for accessing processor resources that are external to a processing device.

Abstract: A digital system is provided with a memory interface converter to couple a memory device that understands a type of command protocol to a memory controller that generates a different type of command protocol. The memory interface converter includes a first memory interface configured to couple to a host controller memory interface having a first signal protocol and a second memory interface configured to couple to one or more memory devices having a different second signal protocol. A decoder is configured to decode commands received on a command input port and to convert the received commands into commands for a command output port. A state machine is configured to emulate memory states according to the first signal protocol, and another state machine is configured to emulate memory controller states according to the second signal protocol.